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Disable bf16 flags on RISC-V unless BUILD_BFLOAT16=1

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This commit is contained in:
Chip Kerchner
2025-09-23 15:02:20 +00:00
parent fe5402d82b
commit 3116749717
1 changed files with 9 additions and 0 deletions
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9
driver/others/dynamic_riscv64.c
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@@ -99,6 +99,9 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_IMA_V (1 << 2)
#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
#define RISCV_HWPROBE_EXT_ZFBFMIN (1 << 52)
#define RISCV_HWPROBE_EXT_ZVFBFMIN (1 << 53)
#define RISCV_HWPROBE_EXT_ZVFBFWMA (1 << 54)
#ifndef NR_riscv_hwprobe
#ifndef NR_arch_specific_syscall
@@ -170,6 +173,8 @@ static gotoblas_t* get_coretype(void) {
if (ret == 0) {
#if defined(BUILD_HFLOAT16)
vector_mask = (RISCV_HWPROBE_IMA_V | RISCV_HWPROBE_EXT_ZFH | RISCV_HWPROBE_EXT_ZVFH);
#elif defined(BUILD_BFLOAT16)
vector_mask = (RISCV_HWPROBE_IMA_V | RISCV_HWPROBE_EXT_ZFBFMIN | RISCV_HWPROBE_EXT_ZVFBFMIN | RISCV_HWPROBE_EXT_ZVFBFWMA);
#else
vector_mask = RISCV_HWPROBE_IMA_V;
#endif
@@ -180,6 +185,10 @@ static gotoblas_t* get_coretype(void) {
snprintf(coremsg, sizeof(coremsg), "Cpu support for Zfh+Zvfh extensions required due to BUILD_HFLOAT16=1\n");
openblas_warning(1, coremsg);
return NULL;
#elif defined(BUILD_BFLOAT16)
snprintf(coremsg, sizeof(coremsg), "Cpu support for Zfbfmin+Zvfbfmin+Zvfbfwma extensions required due to BUILD_BFLOAT16=1\n");
openblas_warning(1, coremsg);
return NULL;
#else
if (!(getauxval(AT_HWCAP) & DETECT_RISCV64_HWCAP_ISA_V))
return NULL;