teddygood
ecca5e480d
Add WASM128_GENERIC STRSM and DTRSM kernels
2026-04-16 17:52:37 +09:00
teddygood
2847354ffb
Allow target-specific GEMM and TRSM overrides
2026-04-16 17:52:37 +09:00
Martin Kroeker
70faa9f19d
Merge pull request #5756 from OpenMathLib/issue5267
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Work around miscompilation of the AVX512 ?GEMM kernels by Windows LLVM
2026-04-15 07:58:21 +02:00
Martin Kroeker
c59578f314
fix conditionals
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2026-04-14 21:32:36 +02:00
Martin Kroeker
172f41c818
Merge pull request #5674 from ChipKerchner/fasterRVVEdges
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Improve performance on edges of GEMM for RISC-V
2026-04-11 22:04:21 +02:00
Martin Kroeker
94e053ac10
Work around miscompilation of the AVX512 ?GEMM kernels by Windows LLVM
2026-04-11 19:27:31 +02:00
Henry Chen
6a5d2142f4
Fix dsdot precision for arm/dot.c
2026-04-09 18:11:47 +08:00
Henry Chen
e875a9cdd0
Remove redundant C implemetations from MIPS directories
2026-04-08 13:59:10 +08:00
Chip Kerchner
0a4d6b2e11
Forgot files from previous check-in.
2026-04-02 20:15:32 +00:00
Chip Kerchner
cc1b5794a0
Reduce number of vectors in use from 32 to 24 for last stage of main block - now full LMUL2.
2026-04-02 20:14:57 +00:00
Chip Kerchner
22b7950baa
Use LMUL2 for calculations in main block - just break them apart before last stage.
2026-04-02 16:24:15 +00:00
Chip Kerchner
3b1aef12c7
Use LMUL2 loads in main block.
2026-04-02 13:20:16 +00:00
Chip Kerchner
daa3215fb4
Remove shadow variable.
2026-03-31 14:41:38 +00:00
Chip Kerchner
d69be17b6f
Convert 2X LMUL1 instructions to 1X LMUL2. Improved FP64 GEMM edges - up to more than 3X faster.
2026-03-30 18:50:27 +00:00
Martin Kroeker
0f9f6e4be5
Merge pull request #5710 from martin-frbg/issue5708
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Work around miscompilation of the ARM64 non-SVE DDOT kernel
2026-03-27 22:09:08 +01:00
Martin Kroeker
b8dbc4a1fc
Merge pull request #5716 from yuanjia111/develop
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[ARM64] Add optimized fp16 shgemm kernels for Neoverse N2
2026-03-27 13:36:25 +01:00
yuanjia
e6eba9fa21
Add optimized FP16 shgemm for for NEOVERSEN2 target
2026-03-27 17:55:06 +08:00
Murray Steele
f6d4fe703b
Fix incorrect cast from BF16 to FP32 in SBGEMM
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This change fixes a regression in SBGEMM where C is assumed to be BF16,
and so unconditionally casts the output to FP32 resulting in incorrect
outputs when beta=1.
2026-03-26 12:10:52 +00:00
Martin Kroeker
e3ce4623c2
Use volatile attribute for SDOT only, to avoid creating new miscompilations
2026-03-24 23:08:02 +01:00
Chip Kerchner
8fc0004024
Fix another typo.
2026-03-24 13:04:54 +00:00
Chip Kerchner
ebf4cd1c6e
Fix typo.
2026-03-22 18:28:21 +00:00
Martin Kroeker
4956446ca2
Merge pull request #5692 from teddygood/wasm-sum-followup
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Enable DSUM SIMD path for WASM128_GENERIC
2026-03-21 12:39:30 +01:00
Martin Kroeker
a89142fd5d
Merge pull request #5688 from martin-frbg/divlimit_dyn
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Make PREFERRED_SIZE, GEMM_DIVIDE_LIMIT and _RATE available to DYNAMIC_ARCH builds
2026-03-20 22:23:15 +01:00
Chip Kerchner
1bb72b223d
Only initialize unused variables to prevent GCC warnings.
2026-03-20 16:00:33 +00:00
Martin Kroeker
0dd501d794
Add GEMM_DIVIDE_RATE and GEMM_PREFERRED_SIZE to parameters
2026-03-20 15:32:06 +01:00
Martin Kroeker
3f6e928d34
Declare result as volatile to keep compilers from optimizing it out
2026-03-20 11:32:23 +01:00
teddygood
f0d142c4dd
Enable DSUM SIMD path for WASM128_GENERIC
2026-03-20 18:39:53 +09:00
Chip Kerchner
a8a00bbf4f
Avoid greater than 4 segment load and store penalties by using 2. Fix mf2 length.
2026-03-19 21:17:20 +00:00
Martin Kroeker
e9aab19bbc
Merge pull request #5689 from teddygood/wasm-sdot-followup
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Use generic dot kernels for WASM128_GENERIC
2026-03-19 17:08:58 +01:00
Chip Kerchner
1e48686df8
Merge remote-tracking branch 'origin/develop' into fasterRVVEdges
2026-03-19 12:15:19 +00:00
Martin Kroeker
8f5e49556f
Add GEMM_DIVIDE_LIMIT to parameters
2026-03-19 08:26:33 +01:00
teddygood
8c3717f69a
Add WASM SIMD widening path for DSDOT
2026-03-19 14:16:18 +09:00
teddygood
6f672df537
Use generic DDOT kernel for WASM128_GENERIC
2026-03-19 14:15:32 +09:00
teddygood
6bb0dbfd3c
Use generic SDOT kernel for WASM128_GENERIC
2026-03-19 13:54:58 +09:00
Martin Kroeker
adba2c3c02
Merge pull request #5685 from teddygood/wasm-intrin-backend-exp
...
Add a WebAssembly SIMD backend for reusable intrinsics kernels
2026-03-18 21:49:53 +01:00
Chip Kerchner
d832ee5086
More global optimzation and clean up.
2026-03-18 13:43:03 +00:00
teddygood
99d05575d0
Enable SAXPY for WebAssembly SIMD backend
2026-03-18 21:27:45 +09:00
teddygood
7ff3588833
Refine WebAssembly SIMD backend scope
2026-03-18 17:24:02 +09:00
Martin Kroeker
79a50d80d3
Fix potential over-optimization by gcc15
2026-03-17 23:13:58 +01:00
Chip Kerchner
477dd40f07
Simplier loops.
2026-03-17 21:18:30 +00:00
teddygood
53d0be88f8
Add WebAssembly SIMD backend for universal intrinsics
2026-03-18 03:23:31 +09:00
Chip Kerchner
79d9fe39c2
Use mf2 instead of m1.
2026-03-17 16:06:54 +00:00
Martin Kroeker
7a95460bb1
Merge pull request #5680 from teddygood/wasm128-generic-target-exp
...
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Add WebAssembly SIMD SGEMM and DGEMM kernels
2026-03-17 14:25:39 +01:00
Martin Kroeker
a1fd7a4658
Merge pull request #5677 from CheryDan/riscv/zdrot
...
Optimize ZROT_RVV for the non-unit-stride case
2026-03-17 11:10:32 +01:00
Chip Kerchner
f927b9448a
Global optimizations.
2026-03-16 21:32:17 +00:00
teddygood
86d1451cbe
Add WebAssembly SIMD GEMM kernels
2026-03-17 05:51:54 +09:00
Chip Kerchner
010f24f961
Better K.
2026-03-16 13:22:31 +00:00
daichengrong
aa967ef6ba
Optimize ZROT_RVV for the non-unit-stride case
...
Optimize the RVV implementation of ZROT when inc_x and inc_y are
non-unit strides (inc_x != 1, inc_y != 1).
Reorder several operations to reduce vector register pressure and
avoid unnecessary vector register spill to the stack. This helps GCC
keep vector values in registers and reduces redundant spill/reload
instructions, improving runtime performance.
No functional change.
Signed-off-by: daichengrong <daichengrong@iscas.ac.cn >
2026-03-16 14:22:54 +08:00
Martin Kroeker
4a888bcb73
set USE_TRMM for WASM
2026-03-15 23:07:16 +01:00
Martin Kroeker
ef3315527f
Don't include the CPUID code in WebAssembly builds
2026-03-15 19:30:13 +01:00
