Support OpenROAD set_dont_touch (#1398)

+ Add calls to `set_dont_touch` and then `unset_dont_touch` at the beginning and end of every resizer script respectively ~ Reorganize config variables
+ Added undocumented variable `RSZ_USE_OLD_REMOVER` to continue to use the old `remove_buffers.py` script instead
~ `LIB_RESIZER_OPT` -> `RSZ_LIB` (with translation behavior)
~ `UNBUFFER_NETS` -> `RSZ_DONT_TOUCH_RX` (with translation behavior)
~ Made timing models only get written after CTS by checking for `STA_PRE_CTS` as well

configuration/general.tcl

@@ -11,24 +11,55 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-set ::env(USE_GPIO_PADS) 0
 
 # General Defaults
 set ::env(CLOCK_PERIOD) "10.0"
+set ::env(USE_GPIO_PADS) 0
+set ::env(RSZ_DONT_TOUCH_RX) "$^"
+
 
 # Flow Controls
-set ::env(RUN_SIMPLE_CTS) 0
-
+set ::env(LEC_ENABLE) 0
+set ::env(YOSYS_REWRITE_VERILOG) 0
 set ::env(FILL_INSERTION) 1
 set ::env(TAP_DECAP_INSERTION) 1
 
+## Intentionally Undocumented
+set ::env(RSZ_USE_OLD_REMOVER) 0
+
+## STA
+set ::env(STA_REPORT_POWER) {1}
+
+## ECO Flow
+set ::env(ECO_ENABLE) {0}
+set ::env(ECO_ITER) {0}
+set ::env(ECO_FINISH) {0}
+set ::env(ECO_SKIP_PIN) {1}
+
+## Routing
 set ::env(RUN_DRT) 1
 set ::env(USE_ARC_ANTENNA_CHECK) 1
 set ::env(RUN_SPEF_EXTRACTION) 1
 set ::env(RUN_IRDROP_REPORT) 1
 
+# 0: no diodes
+# 1: spray inputs with diodes
+# 2: spray inputs with fake diodes first then fix up the violators with real ones
+# 3: use FR Antenna Avoidance flow
+# 4: Spray diodes on design pins, and add diodes where they need to be added for each macro.
+# 5: Same as 2 but behaves like 4.
+set ::env(DIODE_INSERTION_STRATEGY) {3}
+
+## Signoff
+set ::env(RUN_CVC) 1
 set ::env(PRIMARY_SIGNOFF_TOOL) magic
 
+### Netgen
+set ::env(RUN_LVS) 1
+set ::env(LVS_INSERT_POWER_PINS) 1
+set ::env(LVS_CONNECT_BY_LABEL) 0
+
+### Magic-Specific
 set ::env(RUN_MAGIC) 1
 set ::env(RUN_MAGIC_DRC) 1
 set ::env(MAGIC_PAD) 0
@@ -43,6 +74,7 @@ set ::env(MAGIC_INCLUDE_GDS_POINTERS) 0
 set ::env(MAGIC_DISABLE_HIER_GDS) 1
 set ::env(MAGIC_CONVERT_DRC_TO_RDB) 1
 
+### Klayout-Specific
 set ::env(RUN_KLAYOUT) 1
 set ::env(RUN_KLAYOUT_DRC) 0
 set ::env(KLAYOUT_XOR_GDS) 1
@@ -51,27 +83,4 @@ set ::env(TAKE_LAYOUT_SCROT) 0
 set ::env(KLAYOUT_DRC_KLAYOUT_GDS) 0
 set ::env(RUN_KLAYOUT_XOR) 1
 
-set ::env(RUN_CVC) 1
-set ::env(RUN_LVS) 1
-
-set ::env(YOSYS_REWRITE_VERILOG) 0
-set ::env(LEC_ENABLE) 0
-
-set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
-
-
-# 0: no diodes
-# 1: spray inputs with diodes
-# 2: spray inputs with fake diodes first then fix up the violators with real ones
-# 3: use FR Antenna Avoidance flow
-# 4: Spray diodes on design pins, and add diodes where they need to be added for each macro.
-# 5: Same as 2 but behaves like 4.
-set ::env(DIODE_INSERTION_STRATEGY) 3
-
-set ::env(STA_REPORT_POWER) {1}
-
-## ECO Flow
-set ::env(ECO_ENABLE) {0}
-set ::env(ECO_ITER) {0}
-set ::env(ECO_FINISH) {0}
-set ::env(ECO_SKIP_PIN) {1}
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}

configuration/load_order.txt

@@ -1 +1 @@
-general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl lvs.tcl
+general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl

configuration/lvs.tcl

@@ -1,3 +0,0 @@
-set ::env(RUN_LVS) 1
-set ::env(LVS_INSERT_POWER_PINS) 1
-set ::env(LVS_CONNECT_BY_LABEL) 0

configuration/placement.tcl

@@ -38,5 +38,4 @@ set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 1
 set ::env(PL_MAX_DISPLACEMENT_X) 500
 set ::env(PL_MAX_DISPLACEMENT_Y) 100
 set ::env(PL_MACRO_HALO) {0 0}
-set ::env(PL_MACRO_CHANNEL) {0 0}
-set ::env(UNBUFFER_NETS) "^$"
+set ::env(PL_MACRO_CHANNEL) {0 0}

docs/source/reference/configuration.md

@@ -124,6 +124,14 @@ These variables worked initially, but they were too sky130 specific and will be
 | `FP_IO_VMETAL`  | The metal layer on which to place the io pins vertically (sides of the die) <br> (Default: `3`)|
 
 
+### Resizer (Common)
+
+|Variable|Description|
+|-|-|
+| `RSZ_LIB` | Points to the lib file, corresponding to the typical corner, that is used during resizer optimizations. This is copy of `LIB_SYNTH_COMPLETE`. <br> Default: automatically generated in `$::env(synthesis_tmpfiles)/resizer_<library-name>.lib` |
+| `RSZ_DONT_TOUCH_RX` | A single regular expression designating nets as "don't touch" by resizer optimizations. <br> Default: `$^` (matches nothing.) |
+| `LIB_RESIZER_OPT` | **Deprecated: use `RSZ_LIB`**: Points to the lib file, corresponding to the typical corner, that is used during resizer optimizations. This is copy of `LIB_SYNTH_COMPLETE`. <br> Default: automatically generated in `$::env(synthesis_tmpfiles)/resizer_<library-name>.lib` |
+
 ### Placement
 
 |Variable|Description|
@@ -146,7 +154,7 @@ These variables worked initially, but they were too sky130 specific and will be
 | `PL_RESIZER_HOLD_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
 | `PL_RESIZER_SETUP_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `50`)|
 | `PL_RESIZER_ALLOW_SETUP_VIOS` | Allows setup violations when fixing hold. <br> (Default: `0`)|
-| `LIB_RESIZER_OPT` | Points to the lib file, corresponding to the typical corner, that is used during resizer optimizations. This is copy of `LIB_SYNTH_COMPLETE`. <br> Default: `$::env(synthesis_tmpfiles)/resizer_<library-name>.lib` |
+
 | `DONT_USE_CELLS` | The list of cells to not use during resizer optimizations. <br> Default: the contents of `DRC_EXCLUDE_CELL_LIST`. |
 | `PL_ESTIMATE_PARASITICS` | Specifies whether or not to run STA after global placement using OpenROAD's estimate_parasitics -placement and generates reports under `logs/placement`. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
 | `PL_OPTIMIZE_MIRRORING` | Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
@@ -158,8 +166,8 @@ These variables worked initially, but they were too sky130 specific and will be
 | `PL_MACRO_HALO` | Macro placement halo. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`μm). |
 | `PL_MACRO_CHANNEL` | Channel widths between macros. Format: `{Horizontal} {Vertical}` <br> (Default: `0 0`μm). |
 | `MACRO_PLACEMENT_CFG` | Specifies the path a file specifying how openlane should place certain macros |
-| `UNBUFFER_NETS` | A regular expression used to match nets from which to remove buffers after every resizer run. Useful for analog ports in mixed-signal designs where OpenROAD may sometimes add a buffer. <br> (Default: `^$`, matches nothing.) |
-| `DONT_BUFFER_PORTS` | **Removed: Use `UNBUFFER_NETS`.** Semicolon;delimited list of nets from which to remove buffers. <br> (Default: Empty) |
+| `UNBUFFER_NETS` | **Deprecated: Use `RSZ_DONT_TOUCH_RX`** A regular expression used to match nets from which to remove buffers after every resizer run. Useful for analog ports in mixed-signal designs where OpenROAD may sometimes add a buffer. <br> (Default: `^$`, matches nothing.) |
+| `DONT_BUFFER_PORTS` | **Removed: Use `RSZ_DONT_TOUCH_RX`.** Semicolon;delimited list of nets from which to remove buffers. <br> (Default: Empty) |
 
 ### CTS
 
@@ -215,7 +223,7 @@ These variables worked initially, but they were too sky130 specific and will be
 | `GLB_RT_MAXLAYER` | **Removed: Use RT_MAX_LAYER**: The number of highest layer to be used in routing. <br> (Default: `6`)|
 | `GLB_RT_CLOCK_MINLAYER` | **Removed: Use RT_CLOCK_MIN_LAYER**: The number of lowest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MINLAYER`)|
 | `GLB_RT_CLOCK_MAXLAYER` | **Removed: Use RT_CLOCK_MIN_LAYER**: The number of highest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MAXLAYER`)|
-| `GLB_RT_L{1/2/3/4/5/6}_ADJUSTMENT` | **Removed: See PDK variable `GLB_RT_LAYER_ADJUSTMENTS` instead**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to a metal layer in sky130A. Values ranged from 0 to 1 |
+| `GLB_RT_L{1/2/3/4/5/6}_ADJUSTMENT` | **Removed: See PDK variable `GRT_LAYER_ADJUSTMENTS` instead**: Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to a metal layer in sky130A. Values ranged from 0 to 1 |
 | `GLB_RT_UNIDIRECTIONAL` | **Removed**: Allow unidirectional routing. 0 = false, 1 = true <br> (Default: `1`) |
 | `GLB_RT_TILES` | **Removed**: The size of the GCELL used by Fastroute during global routing. <br> (Default: `15`) |
 

flow.tcl

@@ -44,7 +44,9 @@ proc run_cts_step {args} {
 
     run_cts
     run_resizer_timing
-    remove_buffers_from_nets
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
 }
 
 proc run_routing_step {args} {

scripts/openroad/common/io.tcl

@@ -176,7 +176,7 @@ proc write {args} {
         }
     }
 
-    if { [info exists ::env(SAVE_LIB)] } {
+    if { [info exists ::env(SAVE_LIB)] && !$::env(STA_PRE_CTS)} {
         set corners [sta::corners]
         if { [llength $corners] > 1 } {
             puts "Writing timing models for all corners..."

scripts/openroad/common/resizer.tcl

@@ -0,0 +1,49 @@
+# Copyright 2022 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+proc set_dont_touch_rx {net_pattern} {
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        return
+    }
+    if { $net_pattern == {^$} } {
+        # Save some compute
+        return
+    }
+    variable odb_block [[[::ord::get_db] getChip] getBlock]
+    set odb_nets [odb::dbBlock_getNets $::odb_block]
+    foreach net $odb_nets {
+        set net_name [odb::dbNet_getName $net]
+        if { [regexp "$net_pattern" $net_name full] } {
+            puts "\[INFO\] Net '$net_name' matched don't touch regular expression, setting as don't touch..."
+            set_dont_touch "$net_name"
+        }
+    }
+}
+
+proc unset_dont_touch_rx {net_pattern} {
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        return
+    }
+    if { $net_pattern == {^$} } {
+        # Save some compute
+        return
+    }
+    variable odb_block [[[::ord::get_db] getChip] getBlock]
+    set odb_nets [odb::dbBlock_getNets $::odb_block]
+    foreach net $odb_nets {
+        set net_name [odb::dbNet_getName $net]
+        if { [regexp "$net_pattern" $net_name full] } {
+            unset_dont_touch "$net_name"
+        }
+    }
+}

scripts/openroad/resizer.tcl

@@ -12,7 +12,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
-read -override_libs "$::env(LIB_RESIZER_OPT)"
+read -override_libs "$::env(RSZ_LIB)"
 
 unset_propagated_clock [all_clocks]
 
@@ -22,6 +22,11 @@ source $::env(SCRIPTS_DIR)/openroad/common/set_rc.tcl
 # estimate wire rc parasitics
 estimate_parasitics -placement
 
+# set don't touch nets
+source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
+set_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
+# set don't use cells
 if { [info exists ::env(DONT_USE_CELLS)] } {
     set_dont_use $::env(DONT_USE_CELLS)
 }
@@ -65,6 +70,8 @@ if { [catch {check_placement -verbose} errmsg] } {
     exit 1
 }
 
+unset_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
 write
 
 # Run post design optimizations STA

scripts/openroad/resizer_routing_timing.tcl

@@ -12,10 +12,15 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
-read -override_libs "$::env(LIB_RESIZER_OPT)"
+read -override_libs "$::env(RSZ_LIB)"
 
 set_propagated_clock [all_clocks]
 
+# set don't touch nets
+source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
+set_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
+# set don't use cells
 if { [info exists ::env(DONT_USE_CELLS)] } {
     set_dont_use $::env(DONT_USE_CELLS)
 }
@@ -67,6 +72,8 @@ if { [catch {check_placement -verbose} errmsg] } {
     exit 1
 }
 
+unset_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
 write
 
 # Run post timing optimizations STA

scripts/openroad/resizer_timing.tcl

@@ -12,10 +12,15 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
-read -override_libs "$::env(LIB_RESIZER_OPT)"
+read -override_libs "$::env(RSZ_LIB)"
 
 set_propagated_clock [all_clocks]
 
+# set don't touch nets
+source $::env(SCRIPTS_DIR)/openroad/common/resizer.tcl
+set_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
+# set don't use cells
 if { [info exists ::env(DONT_USE_CELLS)] } {
     set_dont_use $::env(DONT_USE_CELLS)
 }
@@ -54,6 +59,8 @@ if { [catch {check_placement -verbose} errmsg] } {
     exit 1
 }
 
+unset_dont_touch_rx "$::env(RSZ_DONT_TOUCH_RX)"
+
 write
 
 # Run post timing optimizations STA

scripts/tcl_commands/all.tcl

@@ -612,6 +612,9 @@ proc prep {args} {
     handle_deprecated_config RUN_ROUTING_DETAILED RUN_DRT; # Why the hell is this even an option?
     handle_deprecated_config SYNTH_CLOCK_UNCERTAINITY SYNTH_CLOCK_UNCERTAINTY;
 
+    handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB;
+    handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX;
+
     #
     ############################
     # Prep directories and files
@@ -725,13 +728,13 @@ proc prep {args} {
             -input $::env(LIB_SYNTH_MERGED)
 
         # trim resizer library
-        if { ! [info exists ::env(LIB_RESIZER_OPT) ] } {
-            set ::env(LIB_RESIZER_OPT) [list]
+        if { ! [info exists ::env(RSZ_LIB) ] } {
+            set ::env(RSZ_LIB) [list]
             foreach lib $::env(LIB_SYNTH_COMPLETE) {
                 set fbasename [file rootname [file tail $lib]]
                 set lib_resizer $::env(synthesis_tmpfiles)/resizer_$fbasename.lib
                 file copy -force $lib $lib_resizer
-                lappend ::env(LIB_RESIZER_OPT) $lib_resizer
+                lappend ::env(RSZ_LIB) $lib_resizer
             }
 
             if { $::env(STD_CELL_LIBRARY_OPT) != $::env(STD_CELL_LIBRARY) } {
@@ -739,7 +742,7 @@ proc prep {args} {
                     set fbasename [file rootname [file tail $lib]]
                     set lib_resizer $::env(synthesis_tmpfiles)/resizer_opt_$fbasename.lib
                     file copy -force $lib $lib_resizer
-                    lappend ::env(LIB_RESIZER_OPT) $lib_resizer
+                    lappend ::env(RSZ_LIB) $lib_resizer
                 }
             }
         }

scripts/tcl_commands/placement.tcl

@@ -178,7 +178,9 @@ proc run_placement {args} {
     }
 
     run_resizer_design
-    remove_buffers_from_nets
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
 
     detailed_placement_or
 
@@ -222,7 +224,7 @@ proc remove_buffers_from_nets {args} {
         -output $save_odb\
         -output_def $save_def\
         -input $::env(CURRENT_ODB)\
-        --match $::env(UNBUFFER_NETS)
+        --match $::env(RSZ_DONT_TOUCH_RX)
 
     set_def $save_def
     set_odb $save_odb
@@ -231,12 +233,4 @@ proc remove_buffers_from_nets {args} {
     exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "remove buffers from nets - openlane"
 }
 
-proc remove_buffers_from_ports {args} {
-    handle_deprecated_command remove_buffers_from_nets
-}
-
-proc remove_buffers {args} {
-    handle_deprecated_command remove_buffers_from_nets
-}
-
 package provide openlane 0.9

scripts/tcl_commands/routing.tcl

@@ -369,7 +369,9 @@ proc run_routing {args} {
     # |----------------------------------------------------|
 
     run_resizer_timing_routing
-    remove_buffers_from_nets
+    if { $::env(RSZ_USE_OLD_REMOVER) == 1} {
+        remove_buffers_from_nets
+    }
 
     if { [info exists ::env(DIODE_CELL)] && ($::env(DIODE_CELL) ne "") } {
         if { ($::env(DIODE_INSERTION_STRATEGY) == 1) || ($::env(DIODE_INSERTION_STRATEGY) == 2) } {