PDK Variable Consistency (#1892)

~ Classified PDK variables by user modifiability ~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT` ~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT` ~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD` - Removed `DEFAULT_MAX_TRAN` from PDK (unused)
2026-05-29 00:23:55 +08:00 · 2023-07-12 17:05:03 +03:00
parent ed5647b8c8
commit 2735f41574
31 changed files with 185 additions and 102 deletions
--- a/configuration/cts.tcl
+++ b/configuration/cts.tcl
@@ -15,7 +15,6 @@
 # cts defaults
 set ::env(RUN_CTS) 1
 set ::env(CTS_MULTICORNER_LIB) 1
-set ::env(CTS_TARGET_SKEW) 200
 set ::env(CTS_TOLERANCE) 100
 set ::env(CTS_SINK_CLUSTERING_SIZE) 25
 set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 50
--- a/configuration/synthesis.tcl
+++ b/configuration/synthesis.tcl
@@ -24,7 +24,6 @@ set ::env(SYNTH_BUFFERING) 1
 set ::env(SYNTH_SPLITNETS) 1
 set ::env(SYNTH_BUFFER_DIRECT_WIRES) 1
 set ::env(SYNTH_SIZING) 0
-set ::env(SYNTH_MAX_FANOUT) 10
 set ::env(SYNTH_STRATEGY) "AREA 0"
 set ::env(SYNTH_ADDER_TYPE) "YOSYS"
 set ::env(CLOCK_BUFFER_FANOUT) 16
--- a/dependencies/tool_metadata.yml
+++ b/dependencies/tool_metadata.yml
@@ -9,7 +9,7 @@
    make install
 - name: magic
  repo: https://github.com/rtimothyedwards/magic
-  commit: 482d7534a27c51d0d1c8a466494680d185d334ee
+  commit: 8b3bb1ae771da1673ac148987466ff31c63513cd
  build: |
    ./configure --prefix=$PREFIX $MAGIC_CONFIG_OPTS
    make clean
@@ -18,7 +18,7 @@
    make install
 - name: netgen
  repo: https://github.com/rtimothyedwards/netgen
-  commit: 28a29504390d53cd3748ff2636be112ef299da0b
+  commit: 87d8759a6980d297edcb9be6f8661867e4726f9a
  build: |
    ./configure --prefix=$PREFIX $MAGIC_CONFIG_OPTS
    make clean
@@ -73,6 +73,6 @@
  in_install: false
 - name: open_pdks
  repo: https://github.com/RTimothyEdwards/open_pdks
-  commit: 3df14f84ab167baf757134739bb1d2c5c044849c
+  commit: 78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc
  in_install: false
  pdk: true
--- a/designs/APU/config.json
+++ b/designs/APU/config.json
@@ -6,7 +6,7 @@
    "FP_CORE_UTIL": 35,
    "CLOCK_PERIOD": 17,
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6
+        "MAX_FANOUT_CONSTRAINT": 6
    },
    "pdk::gf180mcu*": {
        "DIODE_INSERTION_STRATEGY": 4,
--- a/designs/BM64/config.json
+++ b/designs/BM64/config.json
@@ -6,7 +6,7 @@
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 1000 1000",
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "CLOCK_PERIOD": 20,
        "FP_CORE_UTIL": 18
    }
--- a/designs/PPU/config.json
+++ b/designs/PPU/config.json
@@ -7,11 +7,11 @@
    "DPL_CELL_PADDING": 4,
    "FP_CORE_UTIL": 20,
    "pdk::gf180mcu*": {
-        "SYNTH_MAX_FANOUT": 8,
+        "MAX_FANOUT_CONSTRAINT": 8,
        "CLOCK_PERIOD": 18.0
    },
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 8,
+        "MAX_FANOUT_CONSTRAINT": 8,
        "CLOCK_PERIOD": 18.0
    }
 }
--- a/designs/aes_core/config.json
+++ b/designs/aes_core/config.json
@@ -8,7 +8,7 @@
    "DPL_CELL_PADDING": 4,
    "GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT": 60,
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "FP_CORE_UTIL": 25,
        "CLOCK_PERIOD": 21.28,
        "scl::sky130_fd_sc_hd": {
--- a/designs/picorv32a/config.json
+++ b/designs/picorv32a/config.json
@@ -9,7 +9,7 @@
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 35,
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "scl::sky130_fd_sc_ms": {
            "FP_CORE_UTIL": 30
        }
--- a/designs/salsa20/config.json
+++ b/designs/salsa20/config.json
@@ -8,7 +8,7 @@
    "DPL_CELL_PADDING": 4,
    "FP_CORE_UTIL": 20,
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "CLOCK_PERIOD": 36.73,
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 38,
--- a/designs/spm/config.json
+++ b/designs/spm/config.json
@@ -21,7 +21,7 @@
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5
+            "MAX_FANOUT_CONSTRAINT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
@@ -30,7 +30,7 @@
    "pdk::gf180mcu*": {
        "CLOCK_PERIOD": 24.0,
        "FP_CORE_UTIL": 40,
-        "SYNTH_MAX_FANOUT": 4,
+        "MAX_FANOUT_CONSTRAINT": 4,
        "PL_TARGET_DENSITY": 0.5
    }
-}
+}
--- a/designs/usb/config.json
+++ b/designs/usb/config.json
@@ -5,7 +5,7 @@
    "CLOCK_NET": "clk_48",
    "FP_CORE_UTIL": 40,
    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "CLOCK_PERIOD": 12.55,
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 15,
--- a/designs/usb_cdc_core/config.json
+++ b/designs/usb_cdc_core/config.json
@@ -6,7 +6,7 @@
    "pdk::sky130*": {
        "CLOCK_PERIOD": 15.6,
        "FP_CORE_UTIL": 45,
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "scl::sky130_fd_sc_hd": {
            "FP_CORE_UTIL": 30,
            "PL_TARGET_DENSITY": 0.32
--- a/designs/wbqspiflash/config.json
+++ b/designs/wbqspiflash/config.json
@@ -8,12 +8,12 @@
    "DPL_CELL_PADDING": 4,
    "pdk::sky130*": {
        "CLOCK_PERIOD": 18.86,
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "FP_CORE_UTIL": 40,
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 20,
            "SYNTH_STRATEGY": "DELAY 0",
-            "SYNTH_MAX_FANOUT": 4
+            "MAX_FANOUT_CONSTRAINT": 4
        },
        "scl::sky130_fd_sc_hdll": {
            "FP_CORE_UTIL": 40
--- a/designs/xtea/src/xtea.sdc
+++ b/designs/xtea/src/xtea.sdc
@@ -1,11 +1,10 @@
-set_units -time ns
 create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
 set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
 set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
 puts "\[INFO\]: Setting output delay to: $output_delay_value"
 puts "\[INFO\]: Setting input delay to: $input_delay_value"

-set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]

 set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
 set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
@@ -16,7 +15,8 @@ set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [al

 # TODO set this as parameter
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+# fF -> pF
+set cap_load [expr $::env(OUTPUT_CAP_LOAD) / 1000.0] 
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]

--- a/designs/y_huff/config.json
+++ b/designs/y_huff/config.json
@@ -10,7 +10,7 @@
        "FP_SIZING": "absolute",
        "DIE_AREA": "0 0 700 700",
        "CLOCK_PERIOD": 11.35,
-        "SYNTH_MAX_FANOUT": 6
+        "MAX_FANOUT_CONSTRAINT": 6
    },
    "pdk::gf180mcu*": {
        "DIODE_INSERTION_STRATEGY": 3
--- a/designs/zipdiv/config.json
+++ b/designs/zipdiv/config.json
@@ -5,7 +5,7 @@
    "CLOCK_NET": "i_clk",
    "pdk::sky130*": {
        "CLOCK_PERIOD": 20,
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "FP_CORE_UTIL": 40,
        "scl::sky130_fd_sc_hd": {
            "SYNTH_STRATEGY": "DELAY 2"
--- a/docs/source/reference/configuration.md
+++ b/docs/source/reference/configuration.md
@@ -65,10 +65,7 @@ These variables are optional that can be specified in the design configuration f
 |-|-|
 | `SYNTH_AUTONAME` | Add a synthesis step to generate names for instances. This results in instance names that can be very long, but may be more useful than the internal names that are six digit numbers. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
 | `SYNTH_BIN` | The yosys binary used in the flow. <br> (Default: `yosys`) |
-| `SYNTH_CAP_LOAD` | The capacitive load on the output ports in femtofarads. <br> (Default: `33.5` ff)|
 | `SYNTH_DEFINES` | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: NONE) |
-| `SYNTH_MAX_FANOUT`  | The max load that the output ports can drive. <br> (Default: `10` cells) |
-| `SYNTH_MAX_TRAN` | The max transition time (slew) from high to low or low to high on cell inputs in ns. If unset, the library's default maximum transition time will be used. |
 | `SYNTH_CLOCK_UNCERTAINTY`  | Specifies a value for the clock uncertainty/jitter for timing analysis. <br> (Default: `0.25`) |
 | `SYNTH_CLOCK_TRANSITION`  |  Specifies a value for the clock transition /slew for timing analysis. <br> (Default: `0.15`) |
 | `SYNTH_TIMING_DERATE`  | Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing. <br> (Default: `+5%/-5%`) |
@@ -90,7 +87,8 @@ These variables are optional that can be specified in the design configuration f
 | `SYNTH_BUFFER_DIRECT_WIRES` | Insert buffer cells into the design for directly connected wires. <br> (Default: `1`) |
 | `SYNTH_SPLITNETS` | Splits multi-bit nets into single-bit nets. <br> (Default: `1`) |
 | `SYNTH_TOP_LEVEL` | **Deprecated: Use `SYNTH_ELABORATE_ONLY`**: "Elaborate" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. |
-
+| `SYNTH_MAX_FANOUT`  | **Deprecated: Use the PDK's `MAX_FANOUT_CONSTRAINT` value**: The max load that the output ports can drive. |
+| `SYNTH_MAX_TRAN` |  **Deprecated: Use the PDK's `MAX_TRANSITION_CONSTRAINT` value**: The max transition time (slew) from high to low or low to high on cell inputs in ns. If unset, the library's default maximum transition time will be used. |

 ### STA

--- a/docs/source/reference/configuration_files.md
+++ b/docs/source/reference/configuration_files.md
@@ -67,7 +67,7 @@ An minimal demonstrative configuration file would look as follows:
    "CLOCK_PORT": "clk",
    "CLOCK_PERIOD": 100,
    "pdk::sky130A": {
-        "SYNTH_MAX_FANOUT": 6,
+        "MAX_FANOUT_CONSTRAINT": 6,
        "FP_CORE_UTIL": 40,
        "PL_TARGET_DENSITY": "expr::($FP_CORE_UTIL + 5.0) / 100.0",
        "scl::sky130_fd_sc_hd": {
--- a/docs/source/reference/datapoint_definitions.md
+++ b/docs/source/reference/datapoint_definitions.md
@@ -89,7 +89,7 @@
 |---------------|-------------------------------------------------------|
 | `CLOCK_PERIOD`  | The clock period for the design in ns       |
 | `SYNTH_STRATEGY` | Strategies for abc logic synthesis and technology mapping <br> Possible values are "DELAY|AREA 0-3|0-2"; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index. <br> (Default: `AREA 0`)|
-| `SYNTH_MAX_FANOUT`  | The max load that the output ports can drive. <br> (Default: `5` cells) |
+| `MAX_FANOUT_CONSTRAINT`  | The max load that the output ports can drive. <br> (Default: `10` cells) |
 | `FP_CORE_UTIL`  | The core utilization percentage. <br> (Default: `50` percent)|
 | `FP_ASPECT_RATIO`  | The core's aspect ratio (height / width). <br> (Default: `1`)|
 | `FP_PDN_VPITCH`  | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
--- a/docs/source/reference/pdk_configuration.md
+++ b/docs/source/reference/pdk_configuration.md
@@ -6,15 +6,42 @@ flow and its steps.
 All these variables (unless marked optional) are defined by the PDK, but some may
 also be overriden by a user configuration.

-<!--
-    User configurations that should not be modified (unless you 100% know what
-    you're doing) are marked with a double dagger (‡).
-->
-
 ```{note}
 Any examples provided are for the `sky130A` PDK.
 ```

+## User-Modifiable
+
+These values may be modified by the user configuration and the
+included values should be considered "defaults."
+
+| Variable      | Description                                                   |
+|---------------|---------------------------------------------------------------|
+| `FP_PDN_RAIL_OFFSET` | Defines the rail offset for met1 used in PDN. <br> (Example: `0`) |
+| `FP_PDN_HSPACING`  | The spacing between horizontal power/ground pair <br> (Default: `1.7`) |
+| `FP_PDN_VSPACING`  | The spacing between vertical power/ground pair <br> (Default: `1.7`) |
+| `FP_PDN_VOFFSET`  | The offset of the vertical power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.32`) |
+| `FP_PDN_VPITCH`  | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
+| `FP_PDN_HOFFSET`  | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
+| `FP_PDN_HPITCH`  | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
+| `FP_PDN_VWIDTH` | Defines the strap width for the vertical layer used in PDN. <br> (Example: `1.6`) |
+| `FP_PDN_HWIDTH` | Defines the strap width for the horizontal layer used in PDN. <br> (Example: `1.6`) |
+| `FP_PDN_CORE_RING_VWIDTH` | Defines the vertical width for the vertical layer used to create the core ring in the PDN. <br> (Example: `20`) |
+| `FP_PDN_CORE_RING_HWIDTH` | Defines the horizontal width for the horizontal layer used to create the core ring in the PDN. <br> (Example: `20`) |
+| `FP_PDN_CORE_RING_VSPACING` | Defines the spacing for the vertical layer used to create the core ring in the PDN. <br> (Example: `5`) |
+| `FP_PDN_CORE_RING_HSPACING` | Defines the spacing for the horizontal layer used to create the core ring in the PDN. <br> (Example: `5`) |
+| `FP_PDN_CORE_RING_VOFFSET` | Defines the offset for the vertical layer used to create the core ring in the PDN. <br> (Example: `20`) |
+| `FP_PDN_CORE_RING_HOFFSET` | Defines the offset for the horizontal layer used to create the core ring in the PDN. <br> (Example: `20`) |
+| `GRT_LAYER_ADJUSTMENTS` | Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 to 1. <br> (Example: `0.99,0,0,0,0,0`) |
+| `RT_MIN_LAYER`  | The lowest metal layer to route on. <br>(Example: `met1`) |
+| `RT_MAX_LAYER`  | The highest metal layer to route on. <br> (Example: `met5`) |
+| `WIRE_LENGTH_THRESHOLD` | A value in microns above which wire lengths generate warnings, and, if `QUIT_ON_LONG_WIRE` is set, the flow will error out. If a PDK does not set this value, the value is considered to be infinite. (Optional) |
+
+## PDK-Static
+
+These variables should really not be modified unless you absolutely know what
+you're doing.
+
 | Variable      | Description                                                   |
 |---------------|---------------------------------------------------------------|
 | `DEF_UNITS_PER_MICRON` | Defines the unit distance microns. Used during floorplanning for proper def file generation. |
@@ -36,37 +63,51 @@ Any examples provided are for the `sky130A` PDK.
 | `GPIO_PADS_PREFIX` | A list of pad cells name prefixes. |
 | `NETGEN_SETUP_FILE` | Points to the setup file for netgen(lvs), that can exclude certain cells etc.. |
 | `FP_TAPCELL_DIST` | The distance between tapcell columns. Used in floorplanning in tapcell insertion. |
-| `DEFAULT_MAX_TRAN` | Defines the default maximum transition value, used in CTS & synthesis. |
-| `FP_PDN_RAIL_OFFSET` | Defines the rail offset for met1 used in PDN. <br> (Example: `0`) | |
-| `FP_PDN_HSPACING`  | The spacing between horizontal power/ground pair <br> (Default: `1.7`) |
-| `FP_PDN_VSPACING`  | The spacing between vertical power/ground pair <br> (Default: `1.7`) |
-| `FP_PDN_VOFFSET`  | The offset of the vertical power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.32`) |
-| `FP_PDN_VPITCH`  | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
-| `FP_PDN_HOFFSET`  | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
-| `FP_PDN_HPITCH`  | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
-| `FP_PDN_VWIDTH` | Defines the strap width for the vertical layer used in PDN. <br> (Example: `1.6`) | |
-| `FP_PDN_HWIDTH` | Defines the strap width for the horizontal layer used in PDN. <br> (Example: `1.6`) | |
-| `FP_PDN_CORE_RING_VWIDTH` | Defines the vertical width for the vertical layer used to create the core ring in the PDN. <br> (Example: `20`) | |
-| `FP_PDN_CORE_RING_HWIDTH` | Defines the horizontal width for the horizontal layer used to create the core ring in the PDN. <br> (Example: `20`) | |
-| `FP_PDN_CORE_RING_VSPACING` | Defines the spacing for the vertical layer used to create the core ring in the PDN. <br> (Example: `5`) | |
-| `FP_PDN_CORE_RING_HSPACING` | Defines the spacing for the horizontal layer used to create the core ring in the PDN. <br> (Example: `5`) | |
-| `FP_PDN_CORE_RING_VOFFSET` | Defines the offset for the vertical layer used to create the core ring in the PDN. <br> (Example: `20`) | |
-| `FP_PDN_CORE_RING_HOFFSET` | Defines the offset for the horizontal layer used to create the core ring in the PDN. <br> (Example: `20`) | |
-| `WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> (Example: `met1`) ||
-| `GRT_LAYER_ADJUSTMENTS` | Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 to 1. <br> (Example: `0.99,0,0,0,0,0`)
+| `WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> (Example: `met1`) |
 | `FP_IO_HLAYER`  | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Example: `met3`)|
 | `FP_IO_VLAYER`  | The metal layer on which to place the io pins vertically (sides of the die) <br> (Example: `met2`)|
 | `FP_TAPCELL_DIST`  | The horizontal distance between two tapcell columns <br> (Default: `14`) |
-| `RT_MIN_LAYER`  | The lowest metal layer to route on. <br>(Example: `met1`)|
-| `RT_MAX_LAYER`  | The highest metal layer to route on. <br> (Example: `met5`)|
 | `RCX_RULES_MIN` | OpenRCX rules at the minimum corner. (Optional) |
 | `RCX_RULES` | OpenRCX rules at the nominal corner. |
 | `RCX_RULES_MAX` | OpenRCX rules at the maximum corner. (Optional) |
-| `WIRE_LENGTH_THRESHOLD` | A value in microns above which wire lengths generate warnings, and, if `QUIT_ON_LONG_WIRE` is set, the flow will error out. If a PDK does not set this value, the value is considered to be infinite. (Optional) |

 ## SCL-specific variables

-This section defines the necessary variables to configure a standard cell library for use with OpenLane:
+This section defines the necessary variables to configure a standard cell library for use with OpenLane.
+
+### User-modifiable
+
+These values may be modified by the user configuration and the
+included values should be considered "defaults."
+
+| Variable      | Description                                                   |
+|---------------|---------------------------------------------------------------|
+| `MAX_TRANSITION_CONSTRAINT` | Defines the maximum slew (transition) value in ns. |
+| `MAX_FANOUT_CONSTRAINT` | Defines the maximum fanout for a single output in the design. |
+| `OUTPUT_CAP_LOAD` | Defines the capacitive load on the output ports in fF. |
+| `CTS_MAX_CAP` | Defines the maximum capacitance for clock tree synthesis in the design in pF. |
+| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. <br> (Example: `2`) |
+| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells with during detailed placement. This value should not be higher than `GPL_CELL_PADDING` unless you know what you're doing. <br> (Example: `2`) |
+| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
+| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. See [this section](#no-synthesis-cells-file) for more information. |
+| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. See [this section](#drc-exclude-cells-file) for more information. |
+| `FP_PDN_HORIZONTAL_LAYER` | Defines the upper layer used in PDN. |
+| `FP_PDN_VERTICAL_LAYER` | Defines the lower layer used in PDN. |
+| `FP_PDN_RAIL_LAYER` | Defines the rail layer used in PDN. |
+| `FP_PDN_RAIL_WIDTH` | Defines the rail width for the rail layer used in PDN. |
+| `SYNTH_LATCH_MAP` | A pointer for the file containing the latch mapping for yosys. (Optional) |
+| `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. (Optional) |
+| `CARRY_SELECT_ADDER_MAP` | A pointer for the file containing the carry-select adder mapping for Yosys. (Optional) |
+| `RIPPLE_CARRY_ADDER_MAP` | A pointer for the file containing the ripple-carry adder mapping for Yosys. (Optional) |
+| `FULL_ADDER_MAP` | A pointer for the file containing the full adder mapping for Yosys. (Optional) |
+| `SYNTH_CAP_LOAD` | **Deprecated: Use `OUTPUT_CAP_LOAD`**: Defines the capacitive load on the output ports in fF. |
+| `DEFAULT_MAX_TRAN` | **Removed: Use `MAX_TRANSITION_CONSTRAINT`**: Defines the maximum slew (transition) value in ns. |
+
+
+### SCL-static
+
+These variables should really not be modified unless you absolutely know what
+you're doing.

 | Variable      | Description                                                   |
 |---------------|---------------------------------------------------------------|
@@ -84,7 +125,6 @@ This section defines the necessary variables to configure a standard cell librar
 | `SYNTH_DRIVING_CELL_PIN`  | The name of the `SYNTH_DRIVING_CELL`'s output pin. <br>(Default: `Y`)|
 | `SYNTH_CLK_DRIVING_CELL`  | An alternative cell with which to drive clock inputs. Can be left empty, where the SDC script will use `SYNTH_DRIVING_CELL` for clock inputs as well. |
 | `SYNTH_CLK_DRIVING_CELL_PIN`  | The name of the SYNTH_CLK_DRIVING_CELL output pin. Can be left empty, where the SDC script will use `SYNTH_DRIVING_CELL_PIN`. |
-| `SYNTH_CAP_LOAD` | Defines the capacitive load on the output ports in femtofarads. Used in synthesis |
 | `SYNTH_MIN_BUF_PORT` | Defines the buffer, followed by its input port and output port to be used by `ins_buf` statements by yosys. It inserts buffer cells into the design for directly connected wires. <br> (Example: `sky130_fd_sc_hd__buf_2 A X`  )|
 | `SYNTH_TIEHI_PORT` | Defines the tie high cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 HI`)|
 | `SYNTH_TIELO_PORT` | Defines the tie low cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 LO`)|
@@ -93,25 +133,10 @@ This section defines the necessary variables to configure a standard cell librar
 | `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
 | `DIODE_CELL_PIN` | Defines the `DIODE_CELL` pin. This is required if `DIODE_CELL` is defined |
 | `DIODE_CELL` | Defines the diode cell to be used during antenna violations fix step. <br> If this is not defined then the no antenna violations fixes will be attempted |
-| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. <br> (Example: `2`) |
-| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells with during detailed placement. This value should not be higher than `GPL_CELL_PADDING` unless you know what you're doing. <br> (Example: `2`) |
-| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
 | `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
 | `CTS_CLK_BUFFER_LIST` | Defines the list of clock buffers to be used in CTS. |
-| `CTS_MAX_CAP` | Defines the maximum capacitance, used in CTS. |
 | `STD_CELL_POWER_PINS` | Defines power pins of stdcells. Used in PDN. |
 | `STD_CELL_GROUND_PINS` | Defines ground pins of stdcells. Used in PDN. |
-| `FP_PDN_HORIZONTAL_LAYER` | Defines the upper layer used in PDN. |
-| `FP_PDN_VERTICAL_LAYER` | Defines the lower layer used in PDN. |
-| `FP_PDN_RAIL_LAYER` | Defines the rail layer used in PDN. |
-| `FP_PDN_RAIL_WIDTH` | Defines the rail width for the rail layer used in PDN. |
-| `SYNTH_LATCH_MAP` | A pointer for the file containing the latch mapping for yosys. (Optional) |
-| `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. (Optional) |
-| `CARRY_SELECT_ADDER_MAP` | A pointer for the file containing the carry-select adder mapping for Yosys. (Optional) |
-| `RIPPLE_CARRY_ADDER_MAP` | A pointer for the file containing the ripple-carry adder mapping for Yosys. (Optional) |
-| `FULL_ADDER_MAP` | A pointer for the file containing the full adder mapping for Yosys. (Optional) |
-| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. See [this section](#no-synthesis-cells-file) for more information. |
-| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. See [this section](#drc-exclude-cells-file) for more information. |
 | `CVC_SCRIPTS_DIR` | A directory of Circuit Validity Checker (CVC) scripts for the relevant PDK. Must contain the following set of files: `cvcrc`, an initialization file, `cdl.awk`, an awk script to remove black box definitions from SPICE files, `models`, cell models, and finally `power.awk`, an awk script that adds power information to the verilog netlists. |
 | `STD_CELL_LIBRARY_CDL` | A pointer for the cdl view of the SCL. |
 | `LAYERS_RC` | A comma separated list specifying capacitance and resistance per layer. Variable should be provided in the following format. `<layer_name> <capacitance> <resistance>, <layer_name> ...` ([warning](../configuration.md#on-comma-delimited-variables)) (Optional) |
--- a/docs/source/usage/hardening_macros.md
+++ b/docs/source/usage/hardening_macros.md
@@ -55,7 +55,7 @@ These configurations should get you through the flow with the all other configur

 The first decision in synthesis is determining the optimal synthesis strategy `SYNTH_STRATEGY` for your design. For that purpose there is a flag in the `flow.tcl` script, `-synth_explore` that runs a synthesis strategy exploration and reports the results in a table under `<run_path>/reports/`.

-Then you need to consider the best values for the `SYNTH_MAX_FANOUT`.
+Then you need to consider the best values for the `MAX_FANOUT_CONSTRAINT`.

 If your macro is huge (200k+ cells), then you might want to try setting `SYNTH_NO_FLAT` to `1` (Tcl)/`true` (JSON), which will postpone the flattening of the design during synthesis until the very end.

--- a/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv
+++ b/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv
@@ -1,4 +1,4 @@
-design,design_name,config,flow_status,total_runtime,routed_runtime,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_MAX_FANOUT,SYNTH_STRATEGY
+design,design_name,config,flow_status,total_runtime,routed_runtime,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,MAX_FANOUT_CONSTRAINT,SYNTH_STRATEGY
 APU,APU,run_config,flow completed,0h4m26s0ms,0h3m1s0ms,0.0983350472999999,34484.144698225005,36.06,36.0,792.03,3253,0,0,0,0,0,0,0,3,3,0,-1,-1,140372,25964,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,106197908.0,0.0,42.45,43.9,6.23,12.61,0.0,2847,3426,183,703,0,0,0,3120,89,40,102,150,274,250,56,1024,432,424,23,5671,1221,33,2252,3391,12568,88101.99680000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,4.76,17.0,1,35,153.18,153.6,0.3,1,0.4,0,sky130_fd_sc_hd,6,AREA 0
 BM64,BM64,run_config,flow completed,0h21m34s0ms,0h7m10s0ms,1.0,11369.0,10.79,14.0,2185.41,10036,0,0,0,0,0,0,0,54,54,0,-1,-1,1244959,88394,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1127965307.0,0.0,36.41,35.9,7.79,18.11,0.0,8380,12259,21,3896,0,0,0,9910,25,0,9,454,2211,950,347,262,1800,1287,33,64383,13718,3437,20269,11369,113176,965289.5392,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.88,20.0,1,18,153.18,153.6,0.3,1,0.23,0,sky130_fd_sc_hd,6,AREA 0
 PPU,PPU,run_config,flow completed,0h13m54s0ms,0h6m31s0ms,0.733195271625,18162.9649226804,20.49,25.0,2077.11,12649,0,0,0,0,0,0,0,72,65,0,-1,-1,914385,99369,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,640716798.0,0.0,36.57,38.6,7.09,12.5,0.17,5308,8922,576,4178,0,0,0,7674,52,8,53,75,466,113,21,3014,2918,2927,21,43486,10075,708,14399,13317,81985,703299.52,-1,-1,-1,-1,-1,-1,-1,-1,-1,9.05,18.0,1,20,153.18,153.6,0.3,1,0.25,0,sky130_fd_sc_hd,8,AREA 0
--- a/scripts/base.sdc
+++ b/scripts/base.sdc
@@ -10,9 +10,9 @@ set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
 puts "\[INFO\]: Setting output delay to: $output_delay_value"
 puts "\[INFO\]: Setting input delay to: $input_delay_value"

-set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
-if { [info exists ::env(SYNTH_MAX_TRAN)] } {
-    set_max_transition $::env(SYNTH_MAX_TRAN) [current_design]
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+if { [info exists ::env(MAX_TRANSITION_CONSTRAINT)] } {
+    set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
 }

 set clk_input [get_port $::env(CLOCK_PORT)]
@@ -40,7 +40,8 @@ if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
 set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) $all_inputs_wo_clk_rst
 set_driving_cell -lib_cell $::env(SYNTH_CLK_DRIVING_CELL) -pin $::env(SYNTH_CLK_DRIVING_CELL_PIN) $clk_input

-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+# fF -> pF
+set cap_load [expr $::env(OUTPUT_CAP_LOAD) / 1000.0] 
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]

--- a/scripts/compare_regression_reports.py
+++ b/scripts/compare_regression_reports.py
@@ -68,7 +68,7 @@ def cli(
    base_configs = [
        "CLOCK_PERIOD",
        "SYNTH_STRATEGY",
-        "SYNTH_MAX_FANOUT",
+        "MAX_FANOUT_CONSTRAINT",
        "FP_CORE_UTIL",
        "FP_ASPECT_RATIO",
        "FP_PDN_VPITCH",
--- a/scripts/config/config.py
+++ b/scripts/config/config.py
@@ -29,7 +29,7 @@ class ConfigHandler:
    configuration_values = [
        "CLOCK_PERIOD",
        "SYNTH_STRATEGY",
-        "SYNTH_MAX_FANOUT",
+        "MAX_FANOUT_CONSTRAINT",
        "FP_CORE_UTIL",
        "FP_ASPECT_RATIO",
        "FP_PDN_VPITCH",
--- a/scripts/openroad/common/io.tcl
+++ b/scripts/openroad/common/io.tcl
@@ -19,6 +19,41 @@ proc is_blackbox {file_path blackbox_wildcard} {
    return [expr !$not_found]
 }

+proc string_in_file {file_path substring} {
+    set f [open $file_path r]
+    set data [read $f]
+    close $f
+
+    if { [string first $substring $data] != -1} {
+        return 1
+    }
+    return 0
+}
+
+proc env_var_used {file var} {
+    return [string_in_file $file "\$::env($var)"]
+}
+
+proc read_current_sdc {} {
+    if { ![info exists ::env(CURRENT_SDC)]} {
+        puts "\[INFO] CURRENT_SDC not found. Not reading an SDC file."
+        return
+    }
+
+    set ::env(SYNTH_MAX_FANOUT) $::env(MAX_FANOUT_CONSTRAINT)
+    set ::env(SYNTH_CAP_LOAD) $::env(OUTPUT_CAP_LOAD)
+    if { [info exists ::env(MAX_TRANSITION_CONSTRAINT)] } {
+        set ::env(SYNTH_MAX_TRAN) $::env(MAX_TRANSITION_CONSTRAINT)
+    }
+
+    puts "Reading design constraints file at '$::env(CURRENT_SDC)'…"
+    if {[catch {read_sdc $::env(CURRENT_SDC)} errmsg]} {
+        puts stderr $errmsg
+        exit 1
+    }
+}
+
+
 proc read_netlist {args} {
    sta::parse_key_args "read_netlists" args \
        keys {}\
@@ -56,14 +91,27 @@ proc read_netlist {args} {
    link_design $::env(DESIGN_NAME)

    if { [info exists ::env(CURRENT_SDC)] } {
-        if {[catch {read_sdc $::env(CURRENT_SDC)} errmsg]} {
-            puts stderr $errmsg
-            exit 1
-        }
+        read_current_sdc
    }

 }

+
+proc print_units {args} {
+    foreach {unit} {
+        capacitance
+        resistance
+        time
+        voltage
+        current
+        power
+        distance
+    } {
+        set scale [sta::unit_scale $unit]
+        puts "Using [format %.0e $scale] for $unit..."
+    }
+}
+
 proc read_libs {args} {
    sta::parse_key_args "read_libs" args \
        keys {-typical -slowest -fastest}\
@@ -97,6 +145,8 @@ proc read_libs {args} {
            }
        }
    }
+
+    print_units
 }

 proc read {args} {
@@ -139,10 +189,7 @@ proc read {args} {
    read_libs {*}$read_libs_args

    if { [info exists ::env(CURRENT_SDC)] } {
-        if {[catch {read_sdc $::env(CURRENT_SDC)} errmsg]} {
-            puts stderr $errmsg
-            exit 1
-        }
+        read_current_sdc
    }

    if { ![info exist flags(-no_spefs)] } {
--- a/scripts/openroad/cts.tcl
+++ b/scripts/openroad/cts.tcl
@@ -31,8 +31,8 @@ repair_clock_inverters
 puts "\[INFO\]: Configuring cts characterization..."
 set cts_characterization_args [list]
 lappend -max_cap [expr {$::env(CTS_MAX_CAP) * 1e-12}]; # pF -> F
-if { [info exists ::env(SYNTH_MAX_TRAN)] } {
-    lappend -max_slew [expr {$::env(SYNTH_MAX_TRAN) * 1e-9}]; # ns -> S
+if { [info exists ::env(MAX_TRANSITION_CONSTRAINT)] } {
+    lappend -max_slew [expr {$::env(MAX_TRANSITION_CONSTRAINT) * 1e-9}]; # ns -> S
 }
 configure_cts_characterization {*}$cts_characterization_args

--- a/scripts/openroad/sta/multi_corner.tcl
+++ b/scripts/openroad/sta/multi_corner.tcl
@@ -61,9 +61,6 @@ if { $::env(STA_PRE_CTS) } {
    unset_propagated_clock [all_clocks]
 }

-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-
-
 puts "min_report"
 puts "\n==========================================================================="
 puts "report_checks -path_delay min (Hold)"
--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -617,15 +617,20 @@ proc prep {args} {
    set ::env(OPENLANE_VERBOSE) $arg_values(-verbose)

    # DEPRECATED CONFIGS
+    ## PDK
+    handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
+    handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
+    handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
+
    ## Flow
    handle_diode_insertion_strategy

-    handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY;
+    handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY

    handle_deprecated_config VERILATOR_RELATIVE_INCLUDES LINTER_RELATIVE_INCLUDES

-    handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO;
-    handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO;
+    handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO
+    handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO

    handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
    handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX
--- a/scripts/utils/utils.tcl
+++ b/scripts/utils/utils.tcl
@@ -35,6 +35,15 @@ proc handle_deprecated_config {old new} {
    }
 }

+proc handle_deprecated_pdk_config {old new} {
+    if { [info exists ::env($old)] } {
+        puts_warn "$old is now deprecated; use $new instead."
+        set ::env($new) $::env($old)
+        return 1
+    }
+    return 0
+}
+
 proc handle_diode_insertion_strategy {} {
    if { [info exists ::env(DIODE_INSERTION_STRATEGY)] } {
        puts_warn "DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead."
--- a/scripts/yosys/synth.tcl
+++ b/scripts/yosys/synth.tcl
@@ -64,12 +64,15 @@ if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
 set clock_period [expr {$::env(CLOCK_PERIOD) * 1000}]; # ns -> ps

 set driver  $::env(SYNTH_DRIVING_CELL)
-set cload   $::env(SYNTH_CAP_LOAD)
+
+# fF -> pF
+set cap_load $::env(OUTPUT_CAP_LOAD)
+
 # input pin cap of IN_3VX8
-set max_FO $::env(SYNTH_MAX_FANOUT)
+set max_FO $::env(MAX_FANOUT_CONSTRAINT)
 set max_TR 0
-if { [info exist ::env(SYNTH_MAX_TRAN)]} {
-    set max_TR [expr {$::env(SYNTH_MAX_TRAN) * 1000}]; # ns -> ps
+if { [info exist ::env(MAX_TRANSITION_CONSTRAINT)]} {
+    set max_TR [expr {$::env(MAX_TRANSITION_CONSTRAINT) * 1000}]; # ns -> ps
 }


@@ -87,7 +90,7 @@ set CHK_EXT    "chk.rpt"
 set sdc_file $::env(synthesis_tmpfiles)/synthesis.sdc
 set outfile [open ${sdc_file} w]
 puts $outfile "set_driving_cell ${driver}"
-puts $outfile "set_load ${cload}"
+puts $outfile "set_load ${cap_load}"
 close $outfile