Merge pull request #651 from Manarabdelaty/update_rsz_scripts

Update resizer scripts
2026-05-29 00:23:55 +08:00 · 2021-10-19 15:32:22 +02:00
parent 4330fa4eea b7b35ae941
commit 8434170664
20 changed files with 62 additions and 34 deletions
--- a/configuration/README.md
+++ b/configuration/README.md
@@ -109,6 +109,12 @@ These variables are optional that can be specified in the design configuration f
 | `PL_RESIZER_DESIGN_OPTIMIZATIONS` | Specifies whether resizer design optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
 | `PL_RESIZER_TIMING_OPTIMIZATIONS` | Specifies whether resizer timing optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
 | `PL_RESIZER_MAX_WIRE_LENGTH` | Specifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns. <br> (Default: `0`)|
+| `PL_RESIZER_MAX_SLEW_MARGIN` | Specifies a margin for the slews. <br> (Default: `1`)|
+| `PL_RESIZER_MAX_CAP_MARGIN` | Specifies a margin for the capacitances. <br> (Default: `10`)|
+| `PL_RESIZER_HOLD_SLACK_MARGIN` | Specifies a margin for the slack when fixing hold violations. <br> (Default: `0.2`)|
+| `PL_RESIZER_SETUP_SLACK_MARGIN` | Specifies a margin for the slack when fixing setup violations. <br> (Default: `0.2`)|
+| `PL_RESIZER_HOLD_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `30`)|
+| `PL_RESIZER_SETUP_MAX_BUFFER_PERCENT` | Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design. <br> (Default: `30`)|
 | `LIB_OPT` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during OpenPhySyn optimizations. This is usually a trimmed version of `LIB_SLOWEST`. <br> Default: `$::env(TMP_DIR)/opt.lib` |
 | `LIB_RESIZER_OPT` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during resizer optimizations. This is copy of `LIB_SLOWEST`. <br> Default: `$::env(TMP_DIR)/resizer.lib` |
 | `DONT_USE_CELLS` | The list of cells to not use during resizer optimizations. <br> Default: the contents of `DRC_EXCLUDE_CELL_LIST`. |
--- a/configuration/placement.tcl
+++ b/configuration/placement.tcl
@@ -29,3 +29,9 @@ set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 0
 set ::env(PL_OPTIMIZE_MIRRORING) 1
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 1
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 1
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) 10
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.2
+set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) 0.2
+set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 50
+set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) 50
--- a/dependencies/tool_metadata.yml
+++ b/dependencies/tool_metadata.yml
@@ -88,7 +88,7 @@
  in_install: false
 - name: open_pdks
  repo: https://github.com/rtimothyedwards/open_pdks
-  commit: 5cad4f87435ae7f4e17e50d9c66cd79ecc14e663
+  commit: 8d25606b95e3ca3ac20041bcbe42f4237de2906b
  build: ''
  in_install: false
  in_container: false
--- a/designs/s44/config.tcl
+++ b/designs/s44/config.tcl
@@ -15,10 +15,6 @@ set ::env(PL_TARGET_DENSITY) 0.5

 set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl

-# Disable timing checks temporarily till the design configurations are updated 
-# to tackle the timing violations 
-set ::env(QUIT_ON_TIMING_VIOLATIONS) 0
-
 set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
 if { [file exists $filename] == 1} {
 	source $filename
--- a/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl
+++ b/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl
@@ -1,5 +1,5 @@
 # SCL Configs
 set ::env(CLOCK_PERIOD) "10.0"
 set ::env(SYNTH_MAX_FANOUT) 5
-set ::env(FP_CORE_UTIL) 49
+set ::env(FP_CORE_UTIL) 45
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/designs/usb/config.tcl
+++ b/designs/usb/config.tcl
@@ -4,16 +4,9 @@ set ::env(DESIGN_NAME) "usb"

 set ::env(VERILOG_FILES) "./designs/usb/src/usb2p0_core.v"

-set ::env(CLOCK_PERIOD) "15.000"
 set ::env(CLOCK_PORT) "clk_48"
-
-
 set ::env(CLOCK_NET) $::env(CLOCK_PORT)

-# Disable timing checks temporarily till the design configurations are updated 
-# to tackle the timing violations 
-set ::env(QUIT_ON_TIMING_VIOLATIONS) 0
-
 set filename $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
 if { [file exists $filename] == 1} {
 	source $filename
--- a/designs/usb/sky130A_sky130_fd_sc_hd_config.tcl
+++ b/designs/usb/sky130A_sky130_fd_sc_hd_config.tcl
@@ -1,7 +1,8 @@
 # SCL Configs
 set ::env(FP_CORE_UTIL) 40

-set ::env(CLOCK_PERIOD) "12.55"
+set ::env(CLOCK_PERIOD) "15.00"
+set ::env(SYNTH_STRATEGY) "DELAY 0" 
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]

--- a/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl
+++ b/designs/usb_cdc_core/sky130A_sky130_fd_sc_hd_config.tcl
@@ -1,6 +1,6 @@
 # SCL Configs
 set ::env(CLOCK_PERIOD) "15.6"
-set ::env(FP_CORE_UTIL) 45
+set ::env(FP_CORE_UTIL) 30
 set ::env(SYNTH_MAX_FANOUT) 6
-set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(PL_TARGET_DENSITY) "0.32"

--- a/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl
+++ b/designs/wbqspiflash/sky130A_sky130_fd_sc_hd_config.tcl
@@ -1,6 +1,6 @@
 # SCL Configs
 set ::env(CLOCK_PERIOD) "18.86"
-set ::env(FP_CORE_UTIL) 40
-set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 25
+set ::env(SYNTH_MAX_FANOUT) 4
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]

--- a/designs/zipdiv/config.tcl
+++ b/designs/zipdiv/config.tcl
@@ -5,15 +5,9 @@ set ::env(DESIGN_NAME) "zipdiv"
 set ::env(VERILOG_FILES) "./designs/zipdiv/src/zipdiv.v"
 set ::env(SDC_FILE) "./designs/zipdiv/src/zipdiv.sdc"

-set ::env(CLOCK_PERIOD) "2.5"
 set ::env(CLOCK_PORT) "i_clk"
-
-
 set ::env(CLOCK_NET) $::env(CLOCK_PORT)

-# Disable timing checks temporarily till the design configurations are updated 
-# to tackle the timing violations 
-set ::env(QUIT_ON_TIMING_VIOLATIONS) 0

 set filename $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
 if { [file exists $filename] == 1} {
--- a/designs/zipdiv/sky130A_sky130_fd_sc_hd_config.tcl
+++ b/designs/zipdiv/sky130A_sky130_fd_sc_hd_config.tcl
@@ -1,7 +1,9 @@
 # SCL Configs
+set ::env(SYNTH_STRATEGY) "DELAY 2" 
+
 set ::env(GLB_RT_ADJUSTMENT) 0.15

-set ::env(CLOCK_PERIOD) "19.09"
+set ::env(CLOCK_PERIOD) "20.00"
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 40
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/designs/zipdiv/sky130A_sky130_fd_sc_hdll_config.tcl
+++ b/designs/zipdiv/sky130A_sky130_fd_sc_hdll_config.tcl
@@ -1,7 +1,7 @@
 # SCL Configs
 set ::env(GLB_RT_ADJUSTMENT) 0.15

-set ::env(CLOCK_PERIOD) "19.09"
+set ::env(CLOCK_PERIOD) "20.00"
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 40
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/designs/zipdiv/sky130A_sky130_fd_sc_hs_config.tcl
+++ b/designs/zipdiv/sky130A_sky130_fd_sc_hs_config.tcl
@@ -1,7 +1,7 @@
 # SCL Configs
 set ::env(GLB_RT_ADJUSTMENT) 0.15

-set ::env(CLOCK_PERIOD) "19.09"
+set ::env(CLOCK_PERIOD) "20.00"
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 35
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/designs/zipdiv/sky130A_sky130_fd_sc_ls_config.tcl
+++ b/designs/zipdiv/sky130A_sky130_fd_sc_ls_config.tcl
@@ -1,7 +1,7 @@
 # SCL Configs
 set ::env(GLB_RT_ADJUSTMENT) 0.15

-set ::env(CLOCK_PERIOD) "19.09"
+set ::env(CLOCK_PERIOD) "20.00"
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 40
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/designs/zipdiv/sky130A_sky130_fd_sc_ms_config.tcl
+++ b/designs/zipdiv/sky130A_sky130_fd_sc_ms_config.tcl
@@ -1,7 +1,7 @@
 # SCL Configs
 set ::env(GLB_RT_ADJUSTMENT) 0.15

-set ::env(CLOCK_PERIOD) "19.09"
+set ::env(CLOCK_PERIOD) "20.00"
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 35
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
--- a/scripts/openroad/or_cts.tcl
+++ b/scripts/openroad/or_cts.tcl
@@ -71,6 +71,8 @@ detailed_placement
 if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
    optimize_mirroring
 }
+estimate_parasitics -placement
+
 write_def $::env(SAVE_DEF)
 write_sdc $::env(SAVE_SDC)
 if { [check_placement -verbose] } {
--- a/scripts/openroad/or_resizer.tcl
+++ b/scripts/openroad/or_resizer.tcl
@@ -15,6 +15,10 @@
 foreach lib $::env(LIB_RESIZER_OPT) {
    read_liberty $lib
 }
+
+read_liberty -max $::env(LIB_SLOWEST)
+read_liberty -min $::env(LIB_FASTEST)
+
 if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
    puts stderr $errmsg
    exit 1
@@ -47,9 +51,12 @@ if { [info exists ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS)] && $::env(PL_RESIZER_BU
 }

 if { [info exists ::env(PL_RESIZER_MAX_WIRE_LENGTH)] && $::env(PL_RESIZER_MAX_WIRE_LENGTH) } {
-    repair_design -max_wire_length $::env(PL_RESIZER_MAX_WIRE_LENGTH)
+    repair_design -max_wire_length $::env(PL_RESIZER_MAX_WIRE_LENGTH) \
+                  -max_slew_margin $::env(PL_RESIZER_MAX_SLEW_MARGIN) \
+                  -max_cap_margin $::env(PL_RESIZER_MAX_CAP_MARGIN)
 } else {
-    repair_design
+    repair_design -max_slew_margin $::env(PL_RESIZER_MAX_SLEW_MARGIN) \
+                  -max_cap_margin $::env(PL_RESIZER_MAX_CAP_MARGIN)
 }

 report_floating_nets -verbose
--- a/scripts/openroad/or_resizer_routing_timing.tcl
+++ b/scripts/openroad/or_resizer_routing_timing.tcl
@@ -16,6 +16,9 @@ foreach lib $::env(LIB_RESIZER_OPT) {
    read_liberty $lib
 }

+read_liberty -max $::env(LIB_SLOWEST)
+read_liberty -min $::env(LIB_FASTEST)
+
 if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
    puts stderr $errmsg
    exit 1
@@ -43,7 +46,14 @@ global_route
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
 estimate_parasitics -global_routing
 set_propagated_clock [all_clocks]
-repair_timing
+repair_timing -hold \
+              -slack_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN) \
+              -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT)
+
+repair_timing -setup \
+              -slack_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN) \
+              -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT)
+

 # set_placement_padding -global -right $::env(CELL_PAD)
 # set_placement_padding -masters $::env(CELL_PAD_EXCLUDE) -right 0 -left 0
--- a/scripts/openroad/or_resizer_timing.tcl
+++ b/scripts/openroad/or_resizer_timing.tcl
@@ -15,6 +15,10 @@
 foreach lib $::env(LIB_RESIZER_OPT) {
    read_liberty $lib
 }
+
+read_liberty -max $::env(LIB_SLOWEST)
+read_liberty -min $::env(LIB_FASTEST)
+
 if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
    puts stderr $errmsg
    exit 1
@@ -41,7 +45,14 @@ if { [info exists ::env(DONT_USE_CELLS)] } {
 source $::env(SCRIPTS_DIR)/openroad/or_set_rc.tcl 
 estimate_parasitics -placement
 set_propagated_clock [all_clocks]
-repair_timing
+
+repair_timing -hold \
+              -slack_margin $::env(PL_RESIZER_HOLD_SLACK_MARGIN) \
+              -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT)
+
+repair_timing -setup \
+              -slack_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN) \
+              -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT)

 set_placement_padding -global -right $::env(CELL_PAD)

--- a/scripts/tcl_commands/routing.tcl
+++ b/scripts/tcl_commands/routing.tcl
@@ -431,7 +431,7 @@ proc run_resizer_timing_routing {args} {
        TIMER::timer_start
        if { ! [info exists ::env(LIB_RESIZER_OPT) ] } {
            set ::env(LIB_RESIZER_OPT) $::env(TMP_DIR)/resizer.lib
-            file copy -force $::env(LIB_SLOWEST) $::env(LIB_RESIZER_OPT)
+            file copy -force $::env(LIB_SYNTH_COMPLETE) $::env(LIB_RESIZER_OPT)
        }
        if { ! [info exists ::env(DONT_USE_CELLS)] } {
            gen_exclude_list -lib $::env(LIB_RESIZER_OPT) -drc_exclude_only -create_dont_use_list