checkers cleanup

.gitattributes

@@ -0,0 +1,3 @@
+# Settings to improve linguist data reporting (used by GitHub) (copied from Tim Ansell: https://github.com/SymbiFlow/symbiflow-examples/commit/70b13fe74a56dd5ebfa2060c2473050dfff1a0c6#diff-fc723d30b02a4cca7a534518111c1a66)
+*.v                     linguist-language=Verilog
+*.vh                    linguist-language=Verilog

configuration/README.md

@@ -156,8 +156,3 @@ These variables are optional that can be specified in the design configuration f
 |---------------|---------------------------------------------------------------|
 | `CHECK_UNMAPPED_CELLS` | Checks if there are unmapped cells after synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `0`)|
 | `CHECK_ASSIGN_STATEMENTS` | Checks for assign statement in the generated gate level netlist and aborts of any was found.1 = Enabled, 0 = Disabled <br> (Default: `0`)|
-| `CHECK_LATCHES_IN_DESIGN` | Checks for any latches or failures in synthesis and aborts if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
-| `CHECK_DIODE_PLACEMENT` | Checks if there was any failure in legalizing placement after inserting diodes and aborts if any was found.1 = Enabled, 0 = Disabled <br> (Default: `1`)|
-
-
-

configuration/checkers.tcl

@@ -14,7 +14,7 @@
 
 # Synthesis
 set ::env(CHECK_ASSIGN_STATEMENTS) 0
-set ::env(CHECK_LATCHES_IN_DESIGN) 1
+set ::env(CHECK_UNMAPPED_CELLS) 1
 
 # Floor Planning
 

scripts/openroad/or_cts.tcl

@@ -30,12 +30,14 @@ read_sdc $::env(SCRIPTS_DIR)/base.sdc
 set max_slew [expr {$::env(SYNTH_MAX_TRAN) * 1e-9}]; # must convert to seconds
 set max_cap [expr {$::env(CTS_MAX_CAP) * 1e-12}]; # must convert to farad
 
+puts "\[INFO\]: Configuring cts characterization..."
 configure_cts_characterization\
     -max_slew $max_slew\
     -max_cap $max_cap\
     -sqr_cap $::env(CTS_SQR_CAP)\
     -sqr_res $::env(CTS_SQR_RES)
 
+puts "\[INFO\]: Performing clock tree synthesis..."
 clock_tree_synthesis\
     -buf_list $::env(CTS_CLK_BUFFER_LIST)\
     -root_buf $::env(CTS_ROOT_BUFFER)\

scripts/tcl_commands/synthesis.tcl

@@ -94,7 +94,7 @@ proc run_synthesis {args} {
 	check_assign_statements
     }
 
-    if { $::env(CHECK_LATCHES_IN_DESIGN) == 1 } {
+    if { $::env(CHECK_UNMAPPED_CELLS) == 1 } {
 	check_synthesis_failure
     }
 }