Rework Placement (#1684)

+ Add warning when attempting to run Sylvain's script without `DPL_CELL_PADDING` >= 0 + Add warning when DPL_CELL_PADDING is set to greater than GPL_CELL_PADDING ~ Update PDK, changing the default values of GPL/DPL cell padding to `0` ~ **Use $HOME/.volare as the default PDK location** ~ `PL_TARGET_DENSITY` incorporates value of `GPL_CELL_PADDING` in calculation ~ Updated various config files to handle new default padding options ~ CI bugfixes + support for Volare 0.7.1
2026-05-29 00:23:55 +08:00 · 2023-03-22 15:29:01 +02:00
parent 9b77c207f1
commit e5a7a09769
21 changed files with 68 additions and 68 deletions
--- a/.github/workflows/openlane_ci.yml
+++ b/.github/workflows/openlane_ci.yml
@@ -24,16 +24,24 @@ jobs:
      - name: Set up environment variables
        uses: ./.github/actions/set_env_variables

+      - name: Get Volare Build/Push Dependencies
+        run: |
+          # Magic Build Dependencies
+          sudo apt-get install -y tcsh tcl-dev tk-dev libcairo2-dev m4
+          # GHR (Pushing)
+          go get -u github.com/tcnksm/ghr
+
      - name: Build (or Get) PDK
        run: |
+          export PATH=$PATH:$(go env GOPATH)/bin
+          export OPDKS_VER="$(python3 ./dependencies/tool.py open_pdks -f commit)"
          PDK=${{ matrix.pdk }}
          PDK_FAMILY=${PDK%?}
+
          sudo mkdir -p ${{ env.PDK_ROOT }}
          sudo chown -R $USER:$USER ${{ env.PDK_ROOT }}
-          go get -u github.com/tcnksm/ghr
-          export PATH=$PATH:$(go env GOPATH)/bin
+
          python3 -m pip install --upgrade --no-cache-dir volare
-          export OPDKS_VER="$(python3 ./dependencies/tool.py open_pdks -f commit)"
          if [ "${{ secrets.VOLARE_REPO }}" != "" ]; then
            volare enable_or_build\
              --pdk $PDK_FAMILY\
@@ -60,11 +68,6 @@ jobs:
        with:
          name: pdk-tarball-${{ matrix.pdk }}
          path: /tmp/${{ matrix.pdk }}.tar
-
-      - name: Determine If Running Extended Test Set
-        run: |
-          export EVENT_NAME=${{ github.event_name }};
-          python3 ./.github/scripts/determine_test_set.py
  prepare_test_matrices:
    name: Prepare Test Matrices
    runs-on: ubuntu-20.04
@@ -78,6 +81,10 @@ jobs:
      - name: Python Dependencies
        run: |
          python3 -m pip install click pyyaml
+      - name: Determine If Running Extended Test Set
+        run: |
+          export EVENT_NAME=${{ github.event_name }};
+          python3 ./.github/scripts/determine_test_set.py
      - name: Set Matrix
        id: set-matrix
        run: |
--- a/2
+++ b/2
@@ -57,7 +57,7 @@ PRINT_REM_DESIGNS_TIME ?= 0
 SKYWATER_COMMIT ?= $(shell $(PYTHON_BIN) ./dependencies/tool.py sky130 -f commit)
 OPEN_PDKS_COMMIT ?= $(shell $(PYTHON_BIN) ./dependencies/tool.py open_pdks -f commit)

-export PDK_ROOT ?= ./pdks
+export PDK_ROOT ?= $(HOME)/.volare
 export PDK_ROOT := $(shell $(PYTHON_BIN) -c "import os; print(os.path.realpath('$(PDK_ROOT)'), end='')")
 PDK_OPTS = -v $(PDK_ROOT):$(PDK_ROOT) -e PDK_ROOT=$(PDK_ROOT)

--- a/dependencies/tool_metadata.yml
+++ b/dependencies/tool_metadata.yml
@@ -65,6 +65,6 @@
  in_install: false
 - name: open_pdks
  repo: https://github.com/RTimothyEdwards/open_pdks
-  commit: e6f9c8876da77220403014b116761b0b2d79aab4
+  commit: 12df12e2e74145e31c5a13de02f9a1e176b56e67
  in_install: false
  pdk: true
--- a/designs/APU/config.json
+++ b/designs/APU/config.json
@@ -5,15 +5,16 @@
    "CLOCK_NET": "clk",
    "FP_CORE_UTIL": 35,
    "CLOCK_PERIOD": 17,
+    "pdk::sky130*": {
+        "SYNTH_MAX_FANOUT": 6
+    },
    "pdk::gf180mcu*": {
-        "DIODE_INSERTION_STRATEGY": "4",
+        "DIODE_INSERTION_STRATEGY": 4,
+        "GPL_CELL_PADDING": 4,
+        "DPL_CELL_PADDING": 4,
        "PL_RESIZER_HOLD_SLACK_MARGIN": 0.25,
        "FP_CORE_UTIL": 25,
        "PL_RESIZER_HOLD_MAX_BUFFER_PERCENT": 60,
-        "PL_TARGET_DENSITY": 0.31,
        "CLOCK_PERIOD": 75
-    },
-    "pdk::sky130*": {
-        "SYNTH_MAX_FANOUT": 6
    }
 }
--- a/designs/PPU/config.json
+++ b/designs/PPU/config.json
@@ -3,18 +3,15 @@
    "VERILOG_FILES": "dir::src/PPU.v",
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "clk",
+    "GPL_CELL_PADDING": 4,
+    "DPL_CELL_PADDING": 4,
+    "FP_CORE_UTIL": 20,
    "pdk::gf180mcu*": {
-        "FP_CORE_UTIL": 40,
        "SYNTH_MAX_FANOUT": 8,
        "CLOCK_PERIOD": 18.0
    },
    "pdk::sky130*": {
        "SYNTH_MAX_FANOUT": 8,
-        "FP_CORE_UTIL": 20,
-        "PL_TARGET_DENSITY": 0.25,
        "CLOCK_PERIOD": 18.0
-    },
-    "pdk::gf180mcu*": {
-        "PL_TARGET_DENSITY": 0.48
    }
 }
--- a/designs/aes_core/config.json
+++ b/designs/aes_core/config.json
@@ -4,6 +4,8 @@
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "clk",
    "DIODE_INSERTION_STRATEGY": 4,
+    "GPL_CELL_PADDING": 4,
+    "DPL_CELL_PADDING": 4,
    "GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT": 60,
    "pdk::sky130*": {
        "SYNTH_MAX_FANOUT": 6,
--- a/designs/manual_macro_placement_test/config.json
+++ b/designs/manual_macro_placement_test/config.json
@@ -10,6 +10,7 @@
    "BASE_SDC_FILE": "dir::base.sdc",
    "PL_TARGET_DENSITY": 0.35,
    "PL_BASIC_PLACEMENT": 1,
+    "GPL_CELL_PADDING": 0,
    "DPL_CELL_PADDING": 0,
    "CLOCK_PERIOD": 100,
    "CLOCK_PORT": "clk1 clk2",
--- a/designs/picorv32a/config.json
+++ b/designs/picorv32a/config.json
@@ -4,16 +4,14 @@
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "clk",
    "GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
+    "GPL_CELL_PADDING": 2,
+    "DPL_CELL_PADDING": 2,
    "CLOCK_PERIOD": 24,
+    "FP_CORE_UTIL": 35,
    "pdk::sky130*": {
        "SYNTH_MAX_FANOUT": 6,
-        "FP_CORE_UTIL": 35,
        "scl::sky130_fd_sc_ms": {
            "FP_CORE_UTIL": 30
        }
-    },
-    "pdk::gf180mcu*": {
-        "DIODE_PADDING": 0,
-        "PL_TARGET_DENSITY": 0.62
    }
 }
--- a/designs/salsa20/config.json
+++ b/designs/salsa20/config.json
@@ -4,17 +4,15 @@
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "clk",
    "GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
+    "GPL_CELL_PADDING": 4,
+    "DPL_CELL_PADDING": 4,
+    "FP_CORE_UTIL": 20,
    "pdk::sky130*": {
-        "FP_CORE_UTIL": 20,
        "SYNTH_MAX_FANOUT": 6,
        "CLOCK_PERIOD": 36.73,
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 38,
            "PL_RESIZER_HOLD_SLACK_MARGIN": 0.25
        }
-    },
-    "pdk::gf180mcu*": {
-        "DIODE_PADDING": 0,
-        "PL_TARGET_DENSITY": 0.62
    }
 }
--- a/designs/usb/config.json
+++ b/designs/usb/config.json
@@ -14,7 +14,8 @@
    },
    "pdk::gf180mcu*": {
        "CLOCK_PERIOD": 15,
-        "PL_TARGET_DENSITY": 0.5,
-        "DIODE_INSERTION_STRATEGY": "4"
+        "GPL_CELL_PADDING": 4,
+        "DPL_CELL_PADDING": 4,
+        "DIODE_INSERTION_STRATEGY": 3
    }
 }
--- a/designs/usb_cdc_core/config.json
+++ b/designs/usb_cdc_core/config.json
@@ -13,7 +13,9 @@
        }
    },
    "pdk::gf180mcu*": {
-        "DIODE_INSERTION_STRATEGY": "6",
+        "DIODE_INSERTION_STRATEGY": 6,
+        "GPL_CELL_PADDING": 4,
+        "DPL_CELL_PADDING": 4,
        "PL_TARGET_DENSITY": 0.62
    }
 }
--- a/designs/wbqspiflash/config.json
+++ b/designs/wbqspiflash/config.json
@@ -4,6 +4,8 @@
    "CLOCK_PORT": "i_clk",
    "CLOCK_NET": "i_clk",
    "DIODE_INSERTION_STRATEGY": 6,
+    "GPL_CELL_PADDING": 4,
+    "DPL_CELL_PADDING": 4,
    "pdk::sky130*": {
        "CLOCK_PERIOD": 18.86,
        "SYNTH_MAX_FANOUT": 6,
@@ -25,10 +27,5 @@
        "scl::sky130_fd_sc_ms": {
            "FP_CORE_UTIL": 30
        }
-    },
-    "pdk::gf180mcu*": {
-        "DIODE_PADDING": 0,
-        "PL_TARGET_DENSITY": 0.62,
-        "DIODE_INSERTION_STRATEGY": 3
    }
 }
--- a/designs/y_huff/config.json
+++ b/designs/y_huff/config.json
@@ -3,31 +3,16 @@
    "VERILOG_FILES": "dir::src/y_huff.v",
    "CLOCK_PORT": "clk",
    "CLOCK_NET": "clk",
-    "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 700 700",
+    "GPL_CELL_PADDING": 4,
+    "DPL_CELL_PADDING": 4,
+    "FP_CORE_UTIL": 25,
    "pdk::sky130*": {
+        "FP_SIZING": "absolute",
+        "DIE_AREA": "0 0 700 700",
        "CLOCK_PERIOD": 11.35,
-        "SYNTH_MAX_FANOUT": 6,
-        "scl::sky130_fd_sc_hd": {
-            "FP_CORE_UTIL": 40
-        },
-        "scl::sky130_fd_sc_hdll": {
-            "FP_CORE_UTIL": 40
-        },
-        "scl::sky130_fd_sc_hs": {
-            "FP_CORE_UTIL": 30
-        },
-        "scl::sky130_fd_sc_ls": {
-            "FP_CORE_UTIL": 35
-        },
-        "scl::sky130_fd_sc_ms": {
-            "FP_CORE_UTIL": 30
-        }
+        "SYNTH_MAX_FANOUT": 6
    },
    "pdk::gf180mcu*": {
-        "FP_SIZING": "relative",
-        "DIODE_PADDING": 0,
-        "FP_CORE_UTIL": 40,
-        "PL_TARGET_DENSITY": 0.62
+        "DIODE_INSERTION_STRATEGY": 3
    }
 }
--- a/designs/zipdiv/config.json
+++ b/designs/zipdiv/config.json
@@ -18,7 +18,9 @@
        }
    },
    "pdk::gf180mcu*": {
-        "DIODE_INSERTION_STRATEGY": "6",
+        "DIODE_INSERTION_STRATEGY": 6,
+        "GPL_CELL_PADDING": 4,
+        "DPL_CELL_PADDING": 4,
        "PL_TARGET_DENSITY": 0.62
    }
 }
--- a/docs/source/for_developers/pdk_structure.md
+++ b/docs/source/for_developers/pdk_structure.md
@@ -97,8 +97,8 @@ This section defines the necessary variables to configure a standard cell librar
 | `SYNTH_TIELO_PORT` | Defines the tie low cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 LO`)|
 | `FILL_CELL` | Defines the fill cell. Used in fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
 | `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
-| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. Using this is not strictly recommended as you can simply use the density control for global placement. <br> (Example: `0`) |
-| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells lef views with during detailed placement . The number will be integer divided by 2 and placed on both sides. <br> (Example: `4`) |
+| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. <br> (Example: `2`) |
+| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells with during detailed placement. This value should not be higher than `GPL_CELL_PADDING` unless you know what you're doing. <br> (Example: `2`) |
 | `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
 | `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
 | `CTS_CLK_BUFFER_LIST` | Defines the list of clock buffers to be used in CTS. |
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -2,7 +2,7 @@ The OpenLane Documentation
 ==========================
 OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. It also provides a number of custom scripts for design exploration and optimization.

-The flow performs all ASIC implementation steps from RTL all the way down to GDSII. Currently, it supports both A and B variants of the sky130 PDK, but support for the newly released GF180MCU PDK is in the works, and instructions to add support for other (including proprietary) PDKs are documented.
+The flow performs all ASIC implementation steps from RTL all the way down to GDSII. Currently, it supports both A and B variants of the sky130 PDK, the C variant of the gf180mcu PDK, and instructions to add support for other (including proprietary) PDKs are documented.

 OpenLane abstracts the underlying open source utilities, and allows users to configure all their behavior with just a single configuration file.

--- a/docs/source/reference/configuration.md
+++ b/docs/source/reference/configuration.md
@@ -145,7 +145,7 @@ These variables worked initially, but they were too sky130 specific and will be

 |Variable|Description|
 |-|-|
-| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `($::env(FP_CORE_UTIL) +5 ) / 100.0`)|
+| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `($::env(FP_CORE_UTIL) + 10 + (5 * $::env(GPL_CELL_PADDING)) ) / 100.0`)|
 | `PL_TIME_DRIVEN` | Specifies whether the placer should use time driven placement. 0 = false, 1 = true <br> (Default: `1`)|
 | `PL_BASIC_PLACEMENT` | Specifies whether the placer should run basic placement. Basic placement is used for extremely simple, low-density designs of only a few dozens of gates, and should be disabled for most designs. 0 = false, 1 = true <br> (Default: `0`) |
 | `PL_SKIP_INITIAL_PLACEMENT` | Specifies whether the placer should run initial placement or not. 0 = false, 1 = true <br> (Default: `0`) |
--- a/docs/source/reference/datapoint_definitions.md
+++ b/docs/source/reference/datapoint_definitions.md
@@ -94,7 +94,7 @@
 | `FP_ASPECT_RATIO`  | The core's aspect ratio (height / width). <br> (Default: `1`)|
 | `FP_PDN_VPITCH`  | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
 | `FP_PDN_HPITCH`  | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
-| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `0.55`)|
+| `PL_TARGET_DENSITY` | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread <br> (Default: `($::env(FP_CORE_UTIL) + 10 + (5 * $::env(GPL_CELL_PADDING)) ) / 100.0`) |
 | `GRT_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. <br> 1 = most reduction, 0 = least reduction  <br> (Default: `0.2`)|
 | `STD_CELL_LIBRARY` | Specifies the standard cell library used. <br> (Default: `sky130_fd_sc_hd`) |

--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -280,6 +280,8 @@ proc merge_lib {args} {

    parse_key_args "merge_lib" args arg_values $options flags_map $flags

+    puts_verbose "Merging liberty files \{{*}$arg_values(-inputs)\} into \{$arg_values(-output)\}..."
+
    set_if_unset arg_values(-name) "$::env(PDK)_merged"

    try_exec python3 $::env(SCRIPTS_DIR)/mergeLib.py\
@@ -712,7 +714,7 @@ proc prep {args} {
    }

    if { ![info exists ::env(PL_TARGET_DENSITY)] } {
-        set ::env(PL_TARGET_DENSITY) [expr ($::env(FP_CORE_UTIL) + 5.0) / 100.0]
+        set ::env(PL_TARGET_DENSITY) [expr ($::env(FP_CORE_UTIL) + 10.0 + (5 * $::env(GPL_CELL_PADDING))) / 100.0]
    }

    set util 	$::env(FP_CORE_UTIL)
--- a/scripts/tcl_commands/placement.tcl
+++ b/scripts/tcl_commands/placement.tcl
@@ -166,6 +166,10 @@ proc run_placement {args} {
        set ::env(PL_TARGET_DENSITY) $::env(PL_TARGET_DENSITY_CELLS)
    }

+    if { $::env(DPL_CELL_PADDING) > $::env(GPL_CELL_PADDING) } {
+        puts_warn "DPL_CELL_PADDING is set higher than GPL_CELL_PADDING ($::env(DPL_CELL_PADDING) > $::env(GPL_CELL_PADDING)). This may result in inconsistent behavior."
+    }
+
    if { $::env(PL_RANDOM_GLB_PLACEMENT) } {
        # useful for very tiny designs
        random_global_placement
--- a/scripts/tcl_commands/routing.tcl
+++ b/scripts/tcl_commands/routing.tcl
@@ -231,6 +231,9 @@ proc ins_diode_cells_1 {args} {
 }

 proc ins_diode_cells_4 {args} {
+    if { $::env(DPL_CELL_PADDING) == 0 } {
+        puts_warn "DPL_CELL_PADDING is set to 0. Diode insertion strategies 4, 5 and 6 may not function properly."
+    }
    increment_index
    TIMER::timer_start
    set log [index_file $::env(routing_logs)/diodes.log]