OpenLane

mirror of https://github.com/The-OpenROAD-Project/OpenLane.git synced 2026-05-29 00:23:55 +08:00

Files

Kareem Farid 0925f7506f Add Tri-State Logic Exception to Synthesis Checks (#1708 )

Fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1701

\~ Move Yosys check quitting entirely to Python script
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)

\+ Add `SYNTH_CHECKS_ALLOW_TRISTATE` that allows tristate buffers in yosys `check`
\~ Fix wrong default value of `RUN_HEURISTIC_DIODE_INSERTION` in documentation
\~ Move Yosys check quitting entirely to Python script, can ignore tristate buffer-related warnings
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)

2023-04-06 13:03:00 +02:00

checkers.tcl

Add Tri-State Logic Exception to Synthesis Checks (#1708 )

2023-04-06 13:03:00 +02:00

cts.tcl

Add CTS_DISTANCE_BETWEEN_BUFFERS option (#1018 )

2022-03-22 12:38:48 +02:00

extraction.tcl

Add Very Early support for GF180MCU + open_pdks Tweaks (#1251 )

2022-08-18 13:38:05 +02:00

floorplan.tcl

Fix variables for setting pin thickness and multiplier (#1539 )