Files
OpenLane/designs/gcd
Kareem Farid 02a096e7af Integrate Verilator (#1760)
+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD
2023-04-19 14:22:25 +02:00
..
2022-07-29 16:03:10 +02:00
2023-04-19 14:22:25 +02:00