latest STA plus changes to fix prima dcalc and read_spef issues, TCL regression added

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

test/prima3.ok

@@ -31,3 +31,55 @@ Path Type: max
                  228.48   slack (MET)
 
 
+Library: asap7_small
+Cell: BUFx2_ASAP7_75t_R
+Arc sense: positive_unate
+Arc type: combinational
+A ^ -> Y ^
+P = 1.00 V = 0.70 T = 25.00
+------- input_net_transition = 59.28
+|       total_output_net_capacitance = 13.54
+|        11.52     23.04
+v      --------------------
+40.00 | 48.68     71.50
+80.00 | 56.23     79.10
+Table value = 56.33
+PVT scale factor = 1.00
+Delay = 56.33
+
+------- input_net_transition = 59.28
+|       total_output_net_capacitance = 13.54
+|        11.52     23.04
+v      --------------------
+40.00 | 53.99     104.08
+80.00 | 54.58     104.40
+Table value = 63.04
+PVT scale factor = 1.00
+Slew = 63.04
+
+.............................................
+
+A v -> Y v
+P = 1.00 V = 0.70 T = 25.00
+------- input_net_transition = 52.93
+|       total_output_net_capacitance = 12.09
+|        11.52     23.04
+v      --------------------
+40.00 | 48.42     67.20
+80.00 | 57.92     76.86
+Table value = 52.43
+PVT scale factor = 1.00
+Delay = 52.43
+
+------- input_net_transition = 52.93
+|       total_output_net_capacitance = 12.09
+|        11.52     23.04
+v      --------------------
+40.00 | 42.77     80.89
+80.00 | 43.84     81.48
+Table value = 45.00
+PVT scale factor = 1.00
+Slew = 45.00
+
+.............................................
+

test/prima3.tcl

@@ -9,3 +9,4 @@ set_propagated_clock {clk1 clk2 clk3}
 read_spef reg1_asap7.spef
 sta::set_delay_calculator prima
 report_checks -fields {input_pins slew} -format full_clock
+report_dcalc -from u1/A -to u1/Y

test/regression_vars.tcl

@@ -166,6 +166,7 @@ record_public_tests {
   report_json2
   suppress_msg
   verilog_attribute
+  verilog_well_supplies
   verilog_specify
   verilog_write_escape
   verilog_unconnected_hpin

test/verilog_well_supplies.ok

@@ -0,0 +1,26 @@
+module top (y,
+    a);
+ output y;
+ input a;
+
+
+ sky130_fd_sc_hd__buf_1 u1 (.A(a),
+    .X(y));
+endmodule
+module top (y,
+    a);
+ output y;
+ input a;
+
+ wire VGND;
+ wire VNB;
+ wire VPB;
+ wire VPWR;
+
+ sky130_fd_sc_hd__buf_1 u1 (.VGND(VGND),
+    .VNB(VNB),
+    .VPB(VPB),
+    .VPWR(VPWR),
+    .A(a),
+    .X(y));
+endmodule

test/verilog_well_supplies.tcl

@@ -0,0 +1,12 @@
+# Check that write_verilog excludes well pins along with power/ground pins.
+source helpers.tcl
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_well_supplies.v
+link_design top
+set verilog_file [make_result_file "verilog_well_supplies.v"]
+write_verilog $verilog_file
+report_file $verilog_file
+
+set verilog_pwr_file [make_result_file "verilog_well_supplies_pwr.v"]
+write_verilog -include_pwr_gnd $verilog_pwr_file
+report_file $verilog_pwr_file

test/verilog_well_supplies.v

@@ -0,0 +1,17 @@
+module top (
+    output y,
+    input  a
+);
+  supply1 VPWR;
+  supply0 VGND;
+  supply1 VPB;
+  supply0 VNB;
+  sky130_fd_sc_hd__buf_1 u1 (
+      .X(y),
+      .A(a),
+      .VPWR(VPWR),
+      .VGND(VGND),
+      .VPB(VPB),
+      .VNB(VNB)
+  );
+endmodule