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@@ -57,7 +57,7 @@ typedef int Stage;
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class WritePathSpice : public WriteSpice
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{
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public:
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WritePathSpice(Path *path,
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WritePathSpice(const Path *path,
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const char *spice_filename,
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const char *subckt_filename,
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const char *lib_subckt_filename,
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@@ -116,24 +116,24 @@ private:
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const Path *stageLoadPath(Stage stage);
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const TimingArc *stageGateArc(Stage stage);
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const TimingArc *stageWireArc(Stage stage);
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Edge *stageGateEdge(Stage stage);
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Edge *stageWireEdge(Stage stage);
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Pin *stageGateInputPin(Stage stage);
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Pin *stageDrvrPin(Stage stage);
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LibertyPort *stageGateInputPort(Stage stage);
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LibertyPort *stageDrvrPort(Stage stage);
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Pin *stageLoadPin(Stage stage);
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const Edge *stageGateEdge(Stage stage);
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const Edge *stageWireEdge(Stage stage);
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const Pin *stageGateInputPin(Stage stage);
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const Pin *stageDrvrPin(Stage stage);
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const LibertyPort *stageGateInputPort(Stage stage);
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const LibertyPort *stageDrvrPort(Stage stage);
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const Pin *stageLoadPin(Stage stage);
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const char *stageGateInputPinName(Stage stage);
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const char *stageDrvrPinName(Stage stage);
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const char *stageLoadPinName(Stage stage);
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LibertyCell *stageLibertyCell(Stage stage);
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Instance *stageInstance(Stage stage);
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const LibertyCell *stageLibertyCell(Stage stage);
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const Instance *stageInstance(Stage stage);
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float findSlew(const Path *path);
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float findSlew(const Path *path,
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const RiseFall *rf,
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const TimingArc *next_arc);
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Path *path_;
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const Path *path_;
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PathExpanded path_expanded_;
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// Input clock waveform cycles.
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int clk_cycle_count_;
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@@ -152,7 +152,7 @@ private:
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////////////////////////////////////////////////////////////////
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void
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writePathSpice(Path *path,
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writePathSpice(const Path *path,
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const char *spice_filename,
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const char *subckt_filename,
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const char *lib_subckt_filename,
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@@ -168,7 +168,7 @@ writePathSpice(Path *path,
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writer.writeSpice();
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}
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WritePathSpice::WritePathSpice(Path *path,
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WritePathSpice::WritePathSpice(const Path *path,
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const char *spice_filename,
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const char *subckt_filename,
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const char *lib_subckt_filename,
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@@ -497,8 +497,8 @@ WritePathSpice::writeGateStage(Stage stage)
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std::string subckt_name = "stage" + std::to_string(stage);
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const Instance *inst = stageInstance(stage);
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LibertyPort *input_port = stageGateInputPort(stage);
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LibertyPort *drvr_port = stageDrvrPort(stage);
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const LibertyPort *input_port = stageGateInputPort(stage);
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const LibertyPort *drvr_port = stageDrvrPort(stage);
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streamPrint(spice_stream_, ".subckt %s %s %s %s\n",
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subckt_name.c_str(),
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@@ -515,7 +515,7 @@ WritePathSpice::writeGateStage(Stage stage)
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const Path *drvr_path = stageDrvrPath(stage);
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const RiseFall *drvr_rf = drvr_path->transition(this);
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Edge *gate_edge = stageGateEdge(stage);
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const Edge *gate_edge = stageGateEdge(stage);
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LibertyPortLogicValues port_values;
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bool is_clked;
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@@ -579,7 +579,7 @@ WritePathSpice::findPathCellNames()
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path_cell_names.insert(cell->name());
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}
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// Include side receivers.
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Pin *drvr_pin = stageDrvrPin(stage);
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const Pin *drvr_pin = stageDrvrPin(stage);
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auto pin_iter = network_->connectedPinIterator(drvr_pin);
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while (pin_iter->hasNext()) {
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const Pin *pin = pin_iter->next();
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@@ -673,49 +673,49 @@ WritePathSpice::stageWireArc(Stage stage)
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return path_expanded_.path(path_index)->prevArc(this);
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}
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Edge *
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const Edge *
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WritePathSpice::stageGateEdge(Stage stage)
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{
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const Path *path = stageDrvrPath(stage);
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return path->prevEdge(this);
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}
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Edge *
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const Edge *
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WritePathSpice::stageWireEdge(Stage stage)
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{
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const Path *path = stageLoadPath(stage);
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return path->prevEdge(this);
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}
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Pin *
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const Pin *
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WritePathSpice::stageGateInputPin(Stage stage)
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{
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const Path *path = stageGateInputPath(stage);
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return path->pin(this);
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}
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LibertyPort *
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const LibertyPort *
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WritePathSpice::stageGateInputPort(Stage stage)
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{
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Pin *pin = stageGateInputPin(stage);
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const Pin *pin = stageGateInputPin(stage);
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return network_->libertyPort(pin);
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}
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Pin *
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const Pin *
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WritePathSpice::stageDrvrPin(Stage stage)
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{
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const Path *path = stageDrvrPath(stage);
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return path->pin(this);
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}
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LibertyPort *
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const LibertyPort *
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WritePathSpice::stageDrvrPort(Stage stage)
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{
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Pin *pin = stageDrvrPin(stage);
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const Pin *pin = stageDrvrPin(stage);
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return network_->libertyPort(pin);
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}
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Pin *
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const Pin *
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WritePathSpice::stageLoadPin(Stage stage)
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{
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const Path *path = stageLoadPath(stage);
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@@ -725,35 +725,35 @@ WritePathSpice::stageLoadPin(Stage stage)
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const char *
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WritePathSpice::stageGateInputPinName(Stage stage)
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{
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Pin *pin = stageGateInputPin(stage);
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const Pin *pin = stageGateInputPin(stage);
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return network_->pathName(pin);
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}
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const char *
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WritePathSpice::stageDrvrPinName(Stage stage)
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{
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Pin *pin = stageDrvrPin(stage);
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const Pin *pin = stageDrvrPin(stage);
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return network_->pathName(pin);
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}
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const char *
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WritePathSpice::stageLoadPinName(Stage stage)
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{
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Pin *pin = stageLoadPin(stage);
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const Pin *pin = stageLoadPin(stage);
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return network_->pathName(pin);
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}
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Instance *
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const Instance *
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WritePathSpice::stageInstance(Stage stage)
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{
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Pin *pin = stageDrvrPin(stage);
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const Pin *pin = stageDrvrPin(stage);
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return network_->instance(pin);
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}
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LibertyCell *
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const LibertyCell *
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WritePathSpice::stageLibertyCell(Stage stage)
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{
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Pin *pin = stageDrvrPin(stage);
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const Pin *pin = stageDrvrPin(stage);
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return network_->libertyPort(pin)->libertyCell();
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}
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