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* Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * updated regression to remove \ from module name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
19 lines
381 B
Plaintext
19 lines
381 B
Plaintext
module multi_sink (clk);
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input clk;
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wire \alu_adder_result_ex[0] ;
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hier_block \h1\x (.childclk(clk),
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.\Y[2:1] ({\alu_adder_result_ex[0] ,
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\alu_adder_result_ex[0] }));
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endmodule
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module hier_block (childclk,
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\Y[2:1] );
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input childclk;
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output [1:0] \Y[2:1] ;
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BUFx2_ASAP7_75t_R \abuf_$100 (.A(childclk));
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BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
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endmodule
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