Deepashree Sengupta eb0446d4e2 Write verilog escape (#394) ...

* Fir for write_verilog issue 3826

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* staToVerilog2 remove escaped_name+=ch

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* updated regression to remove \ from module name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Using helpers.tcl function to redirect results

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* add std::string and remove trailing space, update regression name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* update regression to reflect correct output verilog name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

2026-03-02 16:48:15 -08:00

..

asap7_ccsn.lib.gz

CCSN PR fixes (#178)

2025-01-16 09:35:38 -08:00

asap7_invbuf.lib.gz

…

asap7_seq.lib.gz

prima delay calc

2024-06-30 14:44:31 -07:00

asap7_simple.lib.gz

prima delay calc

2024-06-30 14:44:31 -07:00

asap7_small.lib.gz

test/asap7_small.lib.gz

2024-08-12 20:32:42 -07:00

delay_calc.ok

…

disconnect_mcp_pin.ok

rel 3.0

2026-01-13 09:36:45 -07:00

disconnect_mcp_pin.tcl

disconnect/disconnect pin set_multicycle_path resolves #327

2025-11-13 10:06:57 -07:00

disconnect_mcp_pin.v

disconnect/disconnect pin set_multicycle_path resolves #327

2025-11-13 10:06:57 -07:00

get_filter.ok

Add GitHub Action for CI and fix broken testcases (#391)

2026-02-27 13:51:28 -08:00

get_filter.tcl

Fix for invalid operator error handling (#366)

2026-01-23 11:39:56 -08:00

get_is_buffer.ok

Fix isBuffer (#329)

2025-11-16 15:34:37 -08:00

get_is_buffer.tcl

Fix isBuffer (#329)

2025-11-16 15:34:37 -08:00

get_is_buffer.v

Fix isBuffer (#329)

2025-11-16 15:34:37 -08:00

get_is_memory.ok

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

get_is_memory.tcl

liberty reader rewrite

2026-02-27 17:12:50 -08:00

get_is_memory.v

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

get_lib_pins_of_objects.ok

Add -of_objects key to get_lib_pins (#128)

2024-11-16 14:05:34 -08:00

get_lib_pins_of_objects.tcl

Add -of_objects key to get_lib_pins (#128)

2024-11-16 14:05:34 -08:00

get_noargs.ok

Revisions

2024-09-24 21:20:10 -07:00

get_noargs.tcl

Revisions

2024-09-24 21:20:10 -07:00

get_objrefs.ok

Revisions

2024-09-24 21:20:10 -07:00

get_objrefs.tcl

Revisions

2024-09-24 21:20:10 -07:00

gf180mcu_sram.lib.gz

liberty reader rewrite

2026-02-27 17:12:50 -08:00

helpers.tcl

test/helpers.tcl

2026-02-26 09:32:20 -08:00

liberty_arcs_one2one_1.lib

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_1.ok

liberty reader rewrite

2026-02-27 17:12:50 -08:00

liberty_arcs_one2one_1.tcl

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_1.v

Rename files as requested

2024-08-01 21:14:48 -07:00

liberty_arcs_one2one_2.lib

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_2.ok

liberty reader rewrite

2026-02-27 17:12:50 -08:00

liberty_arcs_one2one_2.tcl

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_2.v

Rename files as requested

2024-08-01 21:14:48 -07:00

liberty_backslash_eol.lib

Allow backslash-EOL to end tokens in Liberty file (#279)

2025-07-31 12:19:36 -07:00

liberty_backslash_eol.ok

Allow backslash-EOL to end tokens in Liberty file (#279)

2025-07-31 12:19:36 -07:00

liberty_backslash_eol.tcl

Allow backslash-EOL to end tokens in Liberty file (#279)

2025-07-31 12:19:36 -07:00

liberty_ccsn.ok

Ignore CCSN groups (#176)

2025-01-15 09:35:40 -08:00

liberty_ccsn.tcl

CCSN PR fixes (#178)

2025-01-16 09:35:38 -08:00

liberty_float_as_str.lib

Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)

2025-08-01 17:41:56 -07:00

liberty_float_as_str.ok

Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)

2025-08-01 17:41:56 -07:00

liberty_float_as_str.tcl

Allow Liberty floats as strings for voltage_map and capacitive_load_unit (#280)

2025-08-01 17:41:56 -07:00

liberty_latch3.lib

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

liberty_latch3.ok

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

liberty_latch3.tcl

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

mcmm3.ok

rel 3.0

2026-01-13 09:36:45 -07:00

min_max_delays.ok

…

multi_corner.ok

…

package_require.ok

Package require test (#303)

2025-10-04 10:36:22 -07:00

package_require.tcl

Package require test (#303)

2025-10-04 10:36:22 -07:00

path_group_names.ok

Sta::isPathGroupName

2025-10-26 09:23:16 -07:00

path_group_names.tcl

All path groups (#215)

2025-02-12 10:40:43 -08:00

power_json.ok

fix and simplify power_json test

2025-12-20 10:45:17 -07:00

power_json.tcl

rel 3.0

2026-01-13 09:36:45 -07:00

power_vcd.ok

rel 3.0

2026-01-13 09:36:45 -07:00

power.ok

rel 3.0

2026-01-13 09:36:45 -07:00

prima3.ok

Fix for invalid operator error handling (#366)

2026-01-23 11:39:56 -08:00

prima3.tcl

prima3 use asap7_small

2025-12-19 09:40:16 -07:00

reg1_asap7.spef

prima delay calc

2024-06-30 14:44:31 -07:00

reg1_asap7.v

prima delay calc

2024-06-30 14:44:31 -07:00

regression

regression sta_dir

2026-02-27 17:54:32 -08:00

regression_vars.tcl

Write verilog escape (#394)

2026-03-02 16:48:15 -08:00

regression.tcl

rel 3.0

2026-01-13 09:36:45 -07:00

report_checks_sorted.ok

search: fix truncating path ends list if sorting by slack (#291)

2025-09-03 16:45:33 -07:00

report_checks_sorted.tcl

search: fix truncating path ends list if sorting by slack (#291)

2025-09-03 16:45:33 -07:00

report_checks_sorted.v

search: fix truncating path ends list if sorting by slack (#291)

2025-09-03 16:45:33 -07:00

report_checks_src_attr.ok

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_checks_src_attr.tcl

Add src_attr field (#108)

2024-10-15 17:28:52 -07:00

report_json1.ok

Add GitHub Action for CI and fix broken testcases (#391)

2026-02-27 13:51:28 -08:00

report_json1.tcl

report_json1/2.tcl rm redirection

2025-01-15 09:24:53 -07:00

report_json2.ok

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_json2.tcl

report_json1/2.tcl rm redirection

2025-01-15 09:24:53 -07:00

save_ok

fix and simplify power_json test

2025-12-20 10:45:17 -07:00

sdf_delays.ok

…

spef_parasitics.ok

…

suppress_msg.ok

Add GitHub Action for CI and fix broken testcases (#391)

2026-02-27 13:51:28 -08:00

suppress_msg.tcl

Add error/warning suppression with suppress_msg and unsuppress_msg commands (#157)

2025-01-17 11:20:19 -08:00

valgrind.suppress

…

verilog_attribute.ok

…

verilog_attribute.tcl

verilog c++ parser

2025-01-21 18:35:21 -07:00

verilog_attribute.v

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

verilog_specify.ok

Recognize some basic specify blocks and ignore them (#309)

2025-10-12 14:11:00 -07:00

verilog_specify.tcl

Recognize some basic specify blocks and ignore them (#309)

2025-10-12 14:11:00 -07:00

verilog_specify.v

Recognize some basic specify blocks and ignore them (#309)

2025-10-12 14:11:00 -07:00

verilog_write_escape.ok

Write verilog escape (#394)

2026-03-02 16:48:15 -08:00

verilog_write_escape.tcl

Write verilog escape (#394)

2026-03-02 16:48:15 -08:00

verilog_write_escape.v

Write verilog escape (#394)

2026-03-02 16:48:15 -08:00