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eb0446d4e2
* Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * updated regression to remove \ from module name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
11 lines
372 B
Tcl
11 lines
372 B
Tcl
# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
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source helpers.tcl
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read_liberty gf180mcu_sram.lib.gz
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read_liberty asap7_small.lib.gz
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read_verilog verilog_write_escape.v
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link_design multi_sink
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set verilog_file [make_result_file "verilog_write_escape.v"]
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write_verilog $verilog_file
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report_file $verilog_file
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read_verilog $verilog_file
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