mirror of
https://github.com/The-OpenROAD-Project/RePlAce.git
synced 2026-05-30 03:35:07 +08:00
Enable skip_initial_place command / update regression tests
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@@ -1,10 +1,11 @@
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sta::define_cmd_args "global_placement" {
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[-skip_initial_place]\
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[-timing_driven]\
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[-bin_grid_count grid_count]}
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proc global_placement { args } {
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sta::parse_key_args "global_placement" args \
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keys {-bin_grid_count -wire_res -wire_cap -skip_initial_place} flags {-timing_driven}
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keys {-bin_grid_count -wire_res -wire_cap} flags {-skip_initial_place -timing_driven}
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set rep [replace_external]
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@@ -45,7 +46,7 @@ proc global_placement { args } {
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# Initialize RePlAce
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$rep init_replace
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if { [info exists keys(-skip_initial_place)] == false } {
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if { ![info exists flags(-skip_initial_place)] } {
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# initial placement with BiCGSTAB
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$rep place_cell_init_place
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}
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@@ -16,7 +16,7 @@ read_def ${design_dir}/${design}.def
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read_liberty ${lib_dir}/NangateOpenCellLibrary_typical.lib
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read_sdc ${design_dir}/${design}.sdc
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global_placement -timing_driven -wire_res 16 -wire_cap 0.23e-15
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global_placement -skip_initial_place -timing_driven -wire_res 16 -wire_cap 0.23e-15
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set rep [replace_external]
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set fp [open ${exp_folder}/${design}_1_td.rpt w]
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@@ -15,7 +15,7 @@ read_def ${design_dir}/${design}.def
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read_liberty ${lib_dir}/NangateOpenCellLibrary_typical.lib
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read_sdc ${design_dir}/${design}.sdc
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global_placement -timing_driven -wire_res 1.6 -wire_cap 0.23e-15
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global_placement -skip_initial_place -timing_driven -wire_res 1.6 -wire_cap 0.23e-15
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set rep [replace_external]
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set fp [open ${exp_folder}/${design}_2_td.rpt w]
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@@ -15,7 +15,7 @@ read_def ${design_dir}/${design}.def
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read_liberty ${lib_dir}/contest.lib
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read_sdc ${design_dir}/${design}.sdc
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global_placement -timing_driven -wire_res 16 -wire_cap 0.23e-15
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global_placement -skip_initial_place -timing_driven -wire_res 16 -wire_cap 0.23e-15
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set rep [replace_external]
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set fp [open ${exp_folder}/${design}_1_td.rpt w]
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@@ -15,7 +15,7 @@ read_def ${design_dir}/${design}.def
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read_liberty ${lib_dir}/contest.lib
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read_sdc ${design_dir}/${design}.sdc
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global_placement -timing_driven -wire_res 1.6 -wire_cap 0.23e-14
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global_placement -skip_initial_place -timing_driven -wire_res 1.6 -wire_cap 0.23e-14
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set rep [replace_external]
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set fp [open ${exp_folder}/${design}_2_td.rpt w]
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