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Page: Short Users Guide to Chisel
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A Detailed Example Acknowledgements Annotations Extending Chisel and Firrtl BlackBoxes Builtin Operators Bundles and Vecs CS250 Chisel Scala Primer Chisel Developer Stuff Chisel Governance Chisel Introduction Chisel Memories Chisel Tutorial Chisel3 vs Chisel2 ChiselSheet Combinational Circuits Cookbook Datatypes in Chisel Debugging with the Interpreter REPL 1 Debugging with the Interpreter REPL 2 Debugging with the Interpreter REPL 3 Developers Experimental Interval Type Experimental Features FixedPoint Frequently Asked Questions Functional Abstraction Functional Module Creation Hardware Expressible in Chisel Home Installation Preparation Interfaces Bulk Connections Memories Modules Multiple Clock Domains Muxes and Input Selection Polymorphism and Parameterization Ports Printing in Chisel Randomization flags Running Stuff Scala Cheatsheet Scala Things You Should Know Scala land vs. Chisel land Short Users Guide to Chisel State Elements Style Guide Test Coverage Troubleshooting Tutorial Problems Unconnected Wires Useful SBT Commands Width Inference chisel toolchain how to publish intellij setup release notes 17 03 23 release notes 17 04 12 release notes 17 05 03 release notes 17 05 16 release notes 17 05 25 release notes 17 05 30 release notes 17 06 22 release notes 17 07 19 release notes 17 08 16 release notes 17 09 14 release notes 17 09 27 release notes 17 10 06 release notes 17 10 27 release notes 17 11 09 sbt subproject tips and tricks
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Short Users Guide to Chisel
edwardcwang edited this page 2018-09-06 17:27:10 -07:00

This is a brief guide to the Chisel hardware description language. To get started, we recommend looking at this document and the Chisel-tutorial

  1. Introduction
  2. Hardware Expressible in Chisel
  3. Datatypes in Chisel
  4. Combinational Circuits
  5. Builtin Operators
  6. Width Inference
  7. Functional Abstraction
  8. Bundles and Vecs
  9. Ports
  10. Modules
  11. Blackboxes
  12. State Elements
  13. Memories
  14. Interfaces & Bulk Connections
  15. Functional Module Creation
  16. Muxes and Input Selection
  17. Polymorphism and Parameterization
  18. Multiple Clock Domains
  19. Annotations: Extending Chisel and Firrtl
  20. Running stuff
  21. Chisel3 vs Chisel2
  22. Acknowledgements