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mediatek: sync with upsteam target

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coolsnowwolf
2026-03-18 12:28:16 +08:00
parent aac86c3e48
commit bd10e8cb21
50 changed files with 1244 additions and 2386 deletions
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60
target/linux/mediatek/patches-6.12/051-v6.16-hwrng-mtk-Add-struct-device-pointer-to-device-contex.patch Normal file
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@@ -0,0 +1,60 @@
From f9c0c36eefaa8c6ee224634bf9c0b8b4ed87b43a Mon Sep 17 00:00:00 2001
From: Sakari Ailus <sakari.ailus@linux.intel.com>
Date: Thu, 10 Apr 2025 18:22:38 +0300
Subject: [PATCH] hwrng: mtk - Add struct device pointer to device context struct
Add a struct device pointer field to the device's context struct. This
makes using the unsigned long priv pointer in struct hwrng unnecessary, so
remove that one as well.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---
drivers/char/hw_random/mtk-rng.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
--- a/drivers/char/hw_random/mtk-rng.c
+++ b/drivers/char/hw_random/mtk-rng.c
@@ -36,6 +36,7 @@ struct mtk_rng {
void __iomem *base;
struct clk *clk;
struct hwrng rng;
+ struct device *dev;
};
static int mtk_rng_init(struct hwrng *rng)
@@ -85,7 +86,7 @@ static int mtk_rng_read(struct hwrng *rn
struct mtk_rng *priv = to_mtk_rng(rng);
int retval = 0;
- pm_runtime_get_sync((struct device *)priv->rng.priv);
+ pm_runtime_get_sync(priv->dev);
while (max >= sizeof(u32)) {
if (!mtk_rng_wait_ready(rng, wait))
@@ -97,8 +98,8 @@ static int mtk_rng_read(struct hwrng *rn
max -= sizeof(u32);
}
- pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
- pm_runtime_put_sync_autosuspend((struct device *)priv->rng.priv);
+ pm_runtime_mark_last_busy(priv->dev);
+ pm_runtime_put_sync_autosuspend(priv->dev);
return retval || !wait ? retval : -EIO;
}
@@ -112,13 +113,13 @@ static int mtk_rng_probe(struct platform
if (!priv)
return -ENOMEM;
+ priv->dev = &pdev->dev;
priv->rng.name = pdev->name;
#ifndef CONFIG_PM
priv->rng.init = mtk_rng_init;
priv->rng.cleanup = mtk_rng_cleanup;
#endif
priv->rng.read = mtk_rng_read;
- priv->rng.priv = (unsigned long)&pdev->dev;
priv->rng.quality = 900;
priv->clk = devm_clk_get(&pdev->dev, "rng");

72
target/linux/mediatek/patches-6.12/061-v6.19-arm64-dts-mediatek-mt7986-bpi-r3-Change-fan-PWM-valu.patch Normal file
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@@ -0,0 +1,72 @@
From 5f271fe1365b63f67fc384ca8d50d473d09de0d1 Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Date: Tue, 3 Dec 2024 07:33:55 +0300
Subject: [PATCH] arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for
mid speed
Popular cheap PWM fans for this machine, like the ones coming in
heatsink+fan combos will not work properly at the currently defined
medium speed. Trying different pwm setting using a command
echo $value > /sys/devices/platform/pwm-fan/hwmon/hwmon1/pwm1
I found:
pwm1 value fan rotation speed cpu temperature notes
-----------------------------------------------------------------
0 maximal 31.5 Celsius too noisy
40 optimal 35.2 Celsius no noise hearable
95 minimal
above 95 does not rotate 55.5 Celsius
-----------------------------------------------------------------
Thus only cpu-active-high and cpu-active-low modes are usable.
I think this is wrong.
This patch fixes cpu-active-medium settings for bpi-r3 board.
I know, the patch is not ideal as it can break pwm fan for some users.
Likely this is the only official mt7986-bpi-r3 heatsink+fan solution
available on the market.
This patch may not be enough. Users may wants to tweak their thermal_zone0
trip points, thus tuning fan rotation speed depending on cpu temperature.
That can be done on the base of the following example:
=== example =========
# cpu temperature below 25 Celsius degrees, no rotation
echo 25000 > /sys/class/thermal/thermal_zone0/trip_point_4_temp
# cpu temperature in [25..32] Celsius degrees, normal rotation speed
echo 32000 > /sys/class/thermal/thermal_zone0/trip_point_3_temp
# cpu temperature above 50 Celsius degrees, max rotation speed
echo 50000 > /sys/class/thermal/thermal_zone0/trip_point_2_temp
=====================
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Changes from v1 to v2:
* improve patch description
Changes from v2 to v3:
* added question to Frank Wunderlich
Changes from v3 to v4:
* Acked by Frank Wunderlich
---
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -42,7 +42,7 @@
compatible = "pwm-fan";
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
- cooling-levels = <255 96 0>;
+ cooling-levels = <255 40 0>;
pwms = <&pwm 0 10000>;
status = "okay";
};

59
target/linux/mediatek/patches-6.12/070-v7.0-pinctrl-mediatek-enable-ies_present-flag-for-MT798x.patch Normal file
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@@ -0,0 +1,59 @@
From 6da9f0cc2717158857f8b8b9369523d0d6770c07 Mon Sep 17 00:00:00 2001
From: Shiji Yang <yangshiji66@outlook.com>
Date: Sat, 17 Jan 2026 11:04:37 +0800
Subject: [PATCH] pinctrl: mediatek: enable ies_present flag for MT798x
The MT798x series SoCs have IES regiter definitions. I think we
must enable the ies_present flag to correctly configure the pin
input mode.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 2 +-
drivers/pinctrl/mediatek/pinctrl-mt7986.c | 4 ++--
drivers/pinctrl/mediatek/pinctrl-mt7988.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -1019,7 +1019,7 @@ static struct mtk_pin_soc mt7981_data =
.nfuncs = ARRAY_SIZE(mt7981_functions),
.eint_hw = &mt7981_eint_hw,
.gpio_m = 0,
- .ies_present = false,
+ .ies_present = true,
.base_names = mt7981_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -919,7 +919,7 @@ static struct mtk_pin_soc mt7986a_data =
.nfuncs = ARRAY_SIZE(mt7986_functions),
.eint_hw = &mt7986a_eint_hw,
.gpio_m = 0,
- .ies_present = false,
+ .ies_present = true,
.base_names = mt7986_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
@@ -945,7 +945,7 @@ static struct mtk_pin_soc mt7986b_data =
.nfuncs = ARRAY_SIZE(mt7986_functions),
.eint_hw = &mt7986b_eint_hw,
.gpio_m = 0,
- .ies_present = false,
+ .ies_present = true,
.base_names = mt7986_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
--- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
@@ -1515,7 +1515,7 @@ static const struct mtk_pin_soc mt7988_d
.nfuncs = ARRAY_SIZE(mt7988_functions),
.eint_hw = &mt7988_eint_hw,
.gpio_m = 0,
- .ies_present = false,
+ .ies_present = true,
.base_names = mt7988_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,

76
target/linux/mediatek/patches-6.12/119-pinctrl-mediatek-MT7981-some-register-map-fixes.patch Normal file
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@@ -0,0 +1,76 @@
From 2b4d8df6054acb13cae20889c40102c93df2edd6 Mon Sep 17 00:00:00 2001
From: developer <developer@mediatek.com>
Date: Tue, 6 Jan 2026 19:52:11 +0800
Subject: [PATCH] pinctrl: mediatek: MT7981: some register map fixes
Fix mt7981 pinctrl setting mistake including:
1) Wrong pinctrl bits length
2) Wrong pinctrl register offset
Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/52579dd19e62df5aff784462e133e14bfe4a7726
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
@@ -48,7 +48,7 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(11, 11, 5, 0x20, 0x10, 10, 1),
PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
@@ -157,7 +157,7 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
- PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(44, 44, 7, 0x70, 0x10, 8, 1),
PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
@@ -221,8 +221,8 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
@@ -230,9 +230,9 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(11, 11, 5, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(13, 13, 5, 0x10, 0x10, 3, 3),
PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
@@ -244,7 +244,7 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(23, 23, 2, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
@@ -310,7 +310,7 @@ static const struct mtk_pin_field_calc m
PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(20, 20, 2, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),

7
target/linux/mediatek/patches-6.12/171-arm64-dts-mediatek-mt7988a-Add-xsphy-for-ssusb0-pcie2.patch → target/linux/mediatek/patches-6.12/171-v6.16-arm64-dts-mediatek-mt7988-Add-xsphy-for-ssusb0-pcie2.patch
View File

@@ -1,14 +1,15 @@
From 1861c63ba7bb7f8a5145d4ceabcf346f274da61f Mon Sep 17 00:00:00 2001
From 2400b24dfecea9a628f63089bf7eeb9a43b91021 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 22 Apr 2025 15:24:30 +0200
Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for
ssusb0/pcie2
Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2
First usb and third pcie controller on mt7988 need a xs-phy to work
properly.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250422132438.15735-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)

4
target/linux/mediatek/patches-6.12/172-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch → target/linux/mediatek/patches-6.12/172-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-enable-xsphy.patch
View File

@@ -1,4 +1,4 @@
From d326d21a44fbc48663840316c35524002029fbb1 Mon Sep 17 00:00:00 2001
From bb5872c4b6cb0a8687b424b9970b2c3cca2ededd Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 22 Apr 2025 15:24:31 +0200
Subject: [PATCH 29/32] arm64: dts: mediatek: mt7988a-bpi-r4: enable xsphy
@@ -7,6 +7,8 @@ Enable XS-Phy on Bananapi R4 for pcie2.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250422132438.15735-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +-

112
target/linux/mediatek/patches-6.12/174-arm64-dts-mediatek-mt7988-add-spi-controllers.patch
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@@ -1,112 +0,0 @@
From patchwork Sun May 11 14:19:20 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
X-Patchwork-Id: 14084127
From: Frank Wunderlich <linux@fw-web.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers
Date: Sun, 11 May 2025 16:19:20 +0200
Message-ID: <20250511141942.10284-5-linux@fw-web.de>
X-Mailer: git-send-email 2.43.0
In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
References: <20250511141942.10284-1-linux@fw-web.de>
MIME-Version: 1.0
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
From: Frank Wunderlich <frank-w@public-files.de>
Add SPI controllers for mt7988.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -311,6 +311,51 @@
status = "disabled";
};
+ spi0: spi@11007000 {
+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11007000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI0>,
+ <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@11008000 {
+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
+ reg = <0 0x11008000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI1>,
+ <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@11009000 {
+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11009000 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+ <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
lvts: lvts@1100a000 {
compatible = "mediatek,mt7988-lvts-ap";
#thermal-sensor-cells = <1>;

69
target/linux/mediatek/patches-6.12/174-v6.16-arm64-dts-mediatek-mt7988-add-spi-controllers.patch Normal file
View File

@@ -0,0 +1,69 @@
From bf7c2ce439ca811dc1697b4bc19ab57bd8f13be3 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 16 May 2025 20:01:35 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988: add spi controllers
Add SPI controllers for mt7988.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-6-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -311,6 +311,51 @@
status = "disabled";
};
+ spi0: spi@11007000 {
+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11007000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI0>,
+ <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@11008000 {
+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
+ reg = <0 0x11008000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI1>,
+ <&infracfg CLK_INFRA_66M_SPI1_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@11009000 {
+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
+ reg = <0 0x11009000 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_104M_SPI2_BCK>,
+ <&infracfg CLK_INFRA_66M_SPI2_HCK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk",
+ "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
lvts: lvts@1100a000 {
compatible = "mediatek,mt7988-lvts-ap";
#thermal-sensor-cells = <1>;

133
target/linux/mediatek/patches-6.12/175-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-to-soc-dtsi.patch
View File

@@ -1,133 +0,0 @@
From patchwork Sun May 11 14:19:21 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
X-Patchwork-Id: 14084155
From: Frank Wunderlich <linux@fw-web.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 05/14] arm64: dts: mediatek: mt7988: move uart0 and spi1
pins to soc dtsi
Date: Sun, 11 May 2025 16:19:21 +0200
Message-ID: <20250511141942.10284-6-linux@fw-web.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
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linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
From: Frank Wunderlich <frank-w@public-files.de>
In order to use uart0 or spi1 there is only 1 possible pin definition
so move them to soc dtsi to reuse them in other boards and avoiding
conflict if defined twice.
Suggested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 --------------
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -328,13 +328,6 @@
};
};
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0";
- };
- };
-
snfi_pins: snfi-pins {
mux {
function = "flash";
@@ -356,13 +349,6 @@
};
};
- spi1_pins: spi1-pins {
- mux {
- function = "spi";
- groups = "spi1";
- };
- };
-
spi2_pins: spi2-pins {
mux {
function = "spi";
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -209,6 +209,20 @@
"pcie_wake_n3_0";
};
};
+
+ spi1_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
};
pwm: pwm@10048000 {
@@ -244,6 +258,8 @@
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART0_CK>;
clock-names = "baud", "bus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "disabled";
};
@@ -338,6 +354,8 @@
"hclk";
#address-cells = <1>;
#size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
status = "disabled";
};

90
target/linux/mediatek/patches-6.12/175-v6.16-arm64-dts-mediatek-mt7988-move-uart0-and-spi1-pins-t.patch Normal file
View File

@@ -0,0 +1,90 @@
From b9ebd166b006f77cef4530b4bf4a291a112da4f2 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 16 May 2025 20:01:36 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988: move uart0 and spi1 pins to soc
dtsi
In order to use uart0 or spi1 there is only 1 possible pin definition
so move them to soc dtsi to reuse them in other boards and avoiding
conflict if defined twice.
Suggested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-7-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 14 --------------
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -328,13 +328,6 @@
};
};
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0";
- };
- };
-
snfi_pins: snfi-pins {
mux {
function = "flash";
@@ -356,13 +349,6 @@
};
};
- spi1_pins: spi1-pins {
- mux {
- function = "spi";
- groups = "spi1";
- };
- };
-
spi2_pins: spi2-pins {
mux {
function = "spi";
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -209,6 +209,20 @@
"pcie_wake_n3_0";
};
};
+
+ spi1_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
};
pwm: pwm@10048000 {
@@ -244,6 +258,8 @@
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_52M_UART0_CK>;
clock-names = "baud", "bus";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
status = "disabled";
};
@@ -338,6 +354,8 @@
"hclk";
#address-cells = <1>;
#size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
status = "disabled";
};

128
target/linux/mediatek/patches-6.12/176-arm64-dts-mediatek-mt7988-add-cci-node.patch
View File

@@ -1,128 +0,0 @@
From patchwork Sun May 11 14:19:22 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
X-Patchwork-Id: 14084106
From: Frank Wunderlich <linux@fw-web.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 06/14] arm64: dts: mediatek: mt7988: add cci node
Date: Sun, 11 May 2025 16:19:22 +0200
Message-ID: <20250511141942.10284-7-linux@fw-web.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
From: Frank Wunderlich <frank-w@public-files.de>
Add cci devicetree node for cpu frequency scaling.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
1 file changed, 33 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -12,6 +12,35 @@
#address-cells = <2>;
#size-cells = <2>;
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-660000000 {
+ opp-hz = /bits/ 64 <660000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -25,6 +54,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -36,6 +66,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -47,6 +78,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -58,6 +90,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cluster0_opp: opp-table-0 {

86
target/linux/mediatek/patches-6.12/176-v6.17-arm64-dts-mediatek-mt7988-add-cci-node.patch Normal file
View File

@@ -0,0 +1,86 @@
From 0cbdb6d04689f8c05074e348c8e0a42b229ef9a3 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 6 Jul 2025 15:22:03 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988: add cci node
Add cci devicetree node for cpu frequency scaling.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250706132213.20412-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
1 file changed, 33 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -12,6 +12,35 @@
#address-cells = <2>;
#size-cells = <2>;
+ cci: cci {
+ compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";
+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-660000000 {
+ opp-hz = /bits/ 64 <660000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -25,6 +54,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -36,6 +66,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -47,6 +78,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -58,6 +90,7 @@
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cluster0_opp: opp-table-0 {

85
target/linux/mediatek/patches-6.12/177-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-subnodes.patch
View File

@@ -1,85 +0,0 @@
From patchwork Sun May 11 14:19:23 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
X-Patchwork-Id: 14084124
From: Frank Wunderlich <linux@fw-web.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 07/14] arm64: dts: mediatek: mt7988: add phy calibration
efuse subnodes
Date: Sun, 11 May 2025 16:19:23 +0200
Message-ID: <20250511141942.10284-8-linux@fw-web.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
From: Frank Wunderlich <frank-w@public-files.de>
MT7988 contains buildin mt753x switch which needs calibration data from
efuse.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -702,6 +702,22 @@
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
+
+ phy_calibration_p0: calib@940 {
+ reg = <0x940 0x10>;
+ };
+
+ phy_calibration_p1: calib@954 {
+ reg = <0x954 0x10>;
+ };
+
+ phy_calibration_p2: calib@968 {
+ reg = <0x968 0x10>;
+ };
+
+ phy_calibration_p3: calib@97c {
+ reg = <0x97c 0x10>;
+ };
};
clock-controller@15000000 {

42
target/linux/mediatek/patches-6.12/177-v6.16-arm64-dts-mediatek-mt7988-add-phy-calibration-efuse-.patch Normal file
View File

@@ -0,0 +1,42 @@
From e4950b016c727feb0c39ad12cfcb6182c9ef3814 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 16 May 2025 20:01:38 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988: add phy calibration efuse
subnodes
MT7988 contains buildin mt753x switch which needs calibration data from
efuse.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -702,6 +702,22 @@
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
+
+ phy_calibration_p0: calib@940 {
+ reg = <0x940 0x10>;
+ };
+
+ phy_calibration_p1: calib@954 {
+ reg = <0x954 0x10>;
+ };
+
+ phy_calibration_p2: calib@968 {
+ reg = <0x968 0x10>;
+ };
+
+ phy_calibration_p3: calib@97c {
+ reg = <0x97c 0x10>;
+ };
};
clock-controller@15000000 {

98
target/linux/mediatek/patches-6.12/180-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolingmaps.patch
View File

@@ -1,98 +0,0 @@
From patchwork Sun May 11 14:26:50 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <frank-w@public-files.de>
X-Patchwork-Id: 14084133
From: Frank Wunderlich <frank-w@public-files.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 10/14] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and
coolingmaps
Date: Sun, 11 May 2025 16:26:50 +0200
Message-ID: <20250511142655.11007-1-frank-w@public-files.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
Add Fan and cooling maps for Bananpi-R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -12,6 +12,15 @@
stdout-path = "serial0:115200n8";
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 80 128 255>;
+ #cooling-cells = <2>;
+ pwms = <&pwm 0 50000>;
+ status = "okay";
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -73,6 +82,26 @@
type = "active";
};
};
+
+ cooling-maps {
+ map-cpu-active-high {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ map-cpu-active-med {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ map-cpu-active-low {
+ /* active: set fan to cooling level 0 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_low>;
+ };
+ };
};
&i2c0 {

59
target/linux/mediatek/patches-6.12/180-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fan-and-coolin.patch Normal file
View File

@@ -0,0 +1,59 @@
From 0f63e96e2ab422d1d35def1da75d3df299bf503e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 16 May 2025 20:01:41 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: Add fan and coolingmaps
Add Fan and cooling maps for Bananapi-R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-12-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -12,6 +12,15 @@
stdout-path = "serial0:115200n8";
};
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 80 128 255>;
+ #cooling-cells = <2>;
+ pwms = <&pwm 0 50000>;
+ status = "okay";
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -73,6 +82,26 @@
type = "active";
};
};
+
+ cooling-maps {
+ map-cpu-active-high {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ map-cpu-active-med {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ map-cpu-active-low {
+ /* active: set fan to cooling level 0 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_low>;
+ };
+ };
};
&i2c0 {

99
target/linux/mediatek/patches-6.12/181-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-nodes.patch
View File

@@ -1,99 +0,0 @@
From patchwork Sun May 11 14:26:51 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
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X-Patchwork-Submitter: Frank Wunderlich <frank-w@public-files.de>
X-Patchwork-Id: 14084136
Received: from frank-u24 ([194.15.84.99]) by mail.gmx.net (mrgmx104
[212.227.17.168]) with ESMTPSA (Nemesis) id 1MD9XF-1u5YvB0cIj-00FOt5; Sun, 11
May 2025 16:27:04 +0200
From: Frank Wunderlich <frank-w@public-files.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 11/14] arm64: dts: mediatek: mt7988a-bpi-r4: configure
spi-nodes
Date: Sun, 11 May 2025 16:26:51 +0200
Message-ID: <20250511142655.11007-2-frank-w@public-files.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
Configure and enable SPI nodes on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -401,6 +401,38 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand: flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&spi_nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+ };
+};
+
&ssusb1 {
status = "okay";
};

55
target/linux/mediatek/patches-6.12/181-v6.16-arm64-dts-mediatek-mt7988a-bpi-r4-configure-spi-node.patc Normal file
View File

@@ -0,0 +1,55 @@
From 6b7642e9d095d33d8034b8b396a2de9e5ecb25a7 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 16 May 2025 20:01:42 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes
Configure and enable SPI nodes on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20250516180147.10416-13-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -401,6 +401,38 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand: flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&spi_nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+ };
+};
+
&ssusb1 {
status = "okay";
};

68
target/linux/mediatek/patches-6.12/182-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-for-cci.patch
View File

@@ -1,68 +0,0 @@
From patchwork Sun May 11 14:26:52 2025
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Frank Wunderlich <frank-w@public-files.de>
X-Patchwork-Id: 14084137
From: Frank Wunderlich <frank-w@public-files.de>
To: Andrew Lunn <andrew@lunn.ch>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Subject: [PATCH v1 12/14] arm64: dts: mediatek: mt7988a-bpi-r4: add
proc-supply for cci
Date: Sun, 11 May 2025 16:26:52 +0200
Message-ID: <20250511142655.11007-3-frank-w@public-files.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
Felix Fietkau <nbd@nbd.name>
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
Errors-To:
linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
CCI requires proc-supply. Add it on board level.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -40,6 +40,10 @@
};
};
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
&cpu0 {
proc-supply = <&rt5190_buck3>;
};

28
target/linux/mediatek/patches-6.12/182-v6.17-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch Normal file
View File

@@ -0,0 +1,28 @@
From b5a4ad957114b59a74b3e3f598ae0785dd86cd32 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 6 Jul 2025 15:22:06 +0200
Subject: [PATCH] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
CCI requires proc-supply. Add it on board level.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250706132213.20412-12-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -40,6 +40,10 @@
};
};
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
&cpu0 {
proc-supply = <&rt5190_buck3>;
};

53
target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch Normal file
View File

@@ -0,0 +1,53 @@
From 0c74ae06ed6b6c9627712a74ecee4e61bbd4092d Mon Sep 17 00:00:00 2001
From: developer <developer@mediatek.com>
Date: Mon, 19 Jan 2026 21:42:29 +0800
Subject: [PATCH] arm64: dts: mediatek: fix mt7981 spim clock
1) Add spi0/1/2 clock parent setting
2) Fix spi1 clock_sel to CLK_TOP_SPIM_MST_SEL
Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/836034ca0baad57e4c287a62ccc5677c60be0e18
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
@@ -248,6 +248,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2_CK>,
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -262,6 +266,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -273,9 +281,13 @@
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;

21
target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch
View File

@@ -56,7 +56,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
@@ -0,0 +1,60 @@
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
@@ -72,6 +72,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ fragment@0 {
+ target = <&mmc0>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_emmc_51>;
+ pinctrl-1 = <&mmc0_pins_emmc_51>;
@@ -424,7 +426,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
@@ -0,0 +1,58 @@
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
@@ -442,6 +444,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ fragment@0 {
+ target-path = <&mmc0>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_sdcard>;
+ pinctrl-1 = <&mmc0_pins_sdcard>;
@@ -485,7 +489,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
@@ -0,0 +1,81 @@
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
@@ -512,6 +516,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0200000>;
@@ -811,7 +819,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+};
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
@@ -0,0 +1,470 @@
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
@@ -831,13 +839,14 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ "mediatek,mt7988a";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n1 loglevel=8 \
+ bootargs = "console=ttyS0,115200n1 \
+ earlycon=uart8250,mmio32,0x11000000 \
+ pci=pcie_bus_perf";
+ };
+
+ memory {
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x40000000>;
+ device_type = "memory";
+ };
+
+ reg_1p8v: regulator-1p8v {

19
target/linux/mediatek/patches-6.12/189-arm64-dts-mediatek-mt7988a-complete-bpi-r4.patch
View File

@@ -187,12 +187,12 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
/ {
chosen {
stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
+ bootargs = "console=ttyS0,115200n1 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
+ rootdisk-spim-nand = <&ubi_rootfs>;
};
fan: pwm-fan {
@@ -50,6 +54,140 @@
@@ -50,6 +54,141 @@
rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
};
@@ -208,8 +208,9 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
+ led-upgrade = &led_green;
+ };
+
+ memory {
+ memory@40000000 {
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ device_type = "memory";
+ };
+
+ /* SFP1 cage (WAN) */
@@ -333,7 +334,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
};
&cci {
@@ -174,6 +313,10 @@
@@ -174,6 +314,10 @@
color = <LED_COLOR_ID_GREEN>;
};
@@ -344,7 +345,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -265,6 +407,14 @@
@@ -265,6 +408,14 @@
#size-cells = <0>;
reg = <1>;
};
@@ -359,7 +360,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
};
};
@@ -364,34 +514,6 @@
@@ -364,34 +515,6 @@
};
};
@@ -394,7 +395,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
mux {
function = "led";
@@ -399,13 +521,6 @@
@@ -399,13 +522,6 @@
};
};
@@ -408,7 +409,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
mmc0_pins_emmc_45: mmc0-emmc-45-pins {
mux {
function = "flash";
@@ -427,40 +542,12 @@
@@ -427,40 +543,12 @@
};
};
@@ -449,7 +450,7 @@ Subject: [PATCH 32/32] WIP: add BPi-R4
};
&pwm {
@@ -500,6 +587,32 @@
@@ -500,6 +588,32 @@
reg = <0x0 0x200000>;
read-only;
};

136
target/linux/mediatek/patches-6.12/197-dts-mt7986a-bpi-r3-mini-wifi-eeprom.patch
View File

@@ -1,136 +0,0 @@
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
@@ -495,4 +495,133 @@
pinctrl-names = "dbdc";
pinctrl-0 = <&wf_dbdc_pins>, <&wf_led_pins>;
status = "okay";
+
+ mediatek,eeprom-data = <0x86790200 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x125b486c 0x00280000 0x05d00000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x0c000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000012 0x12120000 0x00000000 0x00000000 0x00002222 0x22223333 0x33333333
+ 0x33333333 0x33333333 0x33333333 0x33333333 0x33333333 0x33330000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00292929 0x29282828 0x28282828 0x28282828 0x28282828 0x28282828 0x28000000 0x00000000
+ 0x00000000 0x00242424 0x24222222 0x22242424 0x24222222 0x22242424 0x24222222 0x22242424
+ 0x24222222 0x22000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x007f7f7f 0xd1d1dddd 0xe9e9f5f5 0x01010909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd
+ 0x09091515 0xd1d1dddd 0xe9e9f5f5 0xfdfd0909 0x1515d1d1 0xdddde9e9 0xf5f5fdfd 0x09091515
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0efefc00 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x021e021e 0x02000200 0x02370237 0x02370237
+ 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237 0x02370237
+ 0x02370237 0x02370237 0x02370237 0x02370237 0x002200c6 0xc6c4c4c3 0x0000c1c2 0xc1838383
+ 0x838686c1 0xc1838383 0x838686c2 0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686
+ 0xc1c18181 0x82838585 0x8686c1c1 0x81818283 0x85858686 0xc1c18181 0x82838585 0x8686c5c5
+ 0xc3c100c2 0xc3c2c200 0x81828383 0xc2c2c200 0x81828383 0xc3c1c1c1 0x81828384 0x84c2c2c2
+ 0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c1c1 0xc1818283 0x84848686 0x82828484
+ 0x85868787 0x8989c2c2 0xc2008182 0x83838585 0xc2c2c200 0x81828383 0x8585c2c2 0xc2008182
+ 0x83838585 0xc4c4c2c1 0x00c3c3c3 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c2c2c2
+ 0x00818284 0x84868682 0x82828485 0x8688888b 0x8bc3c3c3 0xc1008183 0x838686c3 0xc3c3c100
+ 0x81838386 0x86c3c3c3 0xc1008183 0x83868600 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00bd0000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00c50000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00495256 0x55555555 0x004a5251 0x51515151 0x004a5355 0x56565656 0x0049504e 0x51515151
+ 0x00495150 0x54545454 0x00495051 0x51515151 0x00495251 0x50505050 0x00495251 0x51515151
+ 0x00495251 0x54545454 0x00495150 0x54545454 0x00495352 0x51515151 0x00495353 0x52525252
+ 0x00495150 0x50505050 0x00495152 0x54545454 0x00495251 0x53535353 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0xd1d1dddd 0xe9e9f5f5 0xfdfd1414 0x1d1d0000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x85840000 0xc3c4c382 0x828281c1 0xc4c5c400 0x0000c1c3 0xc4c4c481 0x8181c1c2 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xc0bbc0bb 0xc0bbc0bb 0x40c5c0c4 0xc0c3c0c3 0x40c340c5 0x40c4c0c3 0x40c3c0c2 0xc0c5c0c4
+ 0x40c440c4 0xc0c3c0c5 0xc0c440c4 0x40c4c0c3 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
+ 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6 0x40c640c6
+ 0x40c640c6 0x40c640c6 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
};

167
target/linux/mediatek/patches-6.12/198-dts-mt7988a-enable-wed.patch Normal file
View File

@@ -0,0 +1,167 @@
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -145,6 +145,32 @@
reg = <0 0x43000000 0 0x50000>;
no-map;
};
+
+ wmcpu_emi: wmcpu-reserved@47cc0000 {
+ reg = <0 0x47cc0000 0 0x00100000>;
+ no-map;
+ };
+
+ wo_emi0: wo-emi@4f600000 {
+ reg = <0 0x4f600000 0 0x40000>;
+ no-map;
+ };
+
+ wo_emi1: wo-emi@4f640000 {
+ reg = <0 0x4f640000 0 0x40000>;
+ no-map;
+ };
+
+ wo_emi2: wo-emi@4f680000 {
+ reg = <0 0x4f680000 0 0x40000>;
+ no-map;
+ };
+
+ wo_data: wo-data@4f700000 {
+ reg = <0 0x4f700000 0 0x800000>;
+ no-map;
+ shared = <1>;
+ };
};
soc {
@@ -867,6 +893,50 @@
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wed0: wed@15010000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15010000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi0>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif0>;
+ mediatek,wo-ilm = <&wo_ilm0>;
+ mediatek,wo-dlm = <&wo_dlm0>;
+ mediatek,wo-cpuboot = <&wo_cpuboot0>;
+ };
+
+ wed1: wed@15012000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15012000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi1>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif1>;
+ mediatek,wo-ilm = <&wo_ilm1>;
+ mediatek,wo-dlm = <&wo_dlm1>;
+ mediatek,wo-cpuboot = <&wo_cpuboot1>;
+ };
+
+ wed2: wed@15014000 {
+ compatible = "mediatek,mt7988-wed",
+ "syscon";
+ reg = <0 0x15014000 0 0x2000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ memory-region = <&wo_emi2>, <&wo_data>;
+ memory-region-names = "wo-emi", "wo-data";
+ mediatek,wo-ccif = <&wo_ccif2>;
+ mediatek,wo-ilm = <&wo_ilm2>;
+ mediatek,wo-dlm = <&wo_dlm2>;
+ mediatek,wo-cpuboot = <&wo_cpuboot2>;
};
switch: switch@15020000 {
@@ -1086,6 +1156,7 @@
<&apmixedsys CLK_APMIXED_SGMPLL>;
mediatek,ethsys = <&ethsys>;
mediatek,infracfg = <&topmisc>;
+ mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1147,6 +1218,72 @@
};
};
+ wo_ccif0: syscon@151a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x151a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif1: syscon@152a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x152a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ccif2: syscon@153a5000 {
+ compatible = "mediatek,mt7988-wo-ccif", "syscon";
+ reg = <0 0x153a5000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wo_ilm0: syscon@151e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x151e0000 0 0x8000>;
+ };
+
+ wo_ilm1: syscon@152e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x152e0000 0 0x8000>;
+ };
+
+ wo_ilm2: syscon@153e0000 {
+ compatible = "mediatek,mt7988-wo-ilm", "syscon";
+ reg = <0 0x153e0000 0 0x8000>;
+ };
+
+ wo_dlm0: syscon@151e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x151e8000 0 0x2000>;
+ };
+
+ wo_dlm1: syscon@152e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x152e8000 0 0x2000>;
+ };
+
+ wo_dlm2: syscon@153e8000 {
+ compatible = "mediatek,mt7988-wo-dlm", "syscon";
+ reg = <0 0x153e8000 0 0x2000>;
+ };
+
+ wo_cpuboot0: syscon@15194000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15194000 0 0x1000>;
+ };
+
+ wo_cpuboot1: syscon@15294000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15294000 0 0x1000>;
+ };
+
+ wo_cpuboot2: syscon@15394000 {
+ compatible = "mediatek,mt7988-wo-cpuboot", "syscon";
+ reg = <0 0x15394000 0 0x1000>;
+ };
+
crypto: crypto@15600000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0 0x15600000 0 0x180000>;

29
target/linux/mediatek/patches-6.12/199-arm64-dts-mediatek-mt7986-increase-ATF-reserved-memo.patch Normal file
View File

@@ -0,0 +1,29 @@
From 236317dd4e55512933dcdaec3d0b4a0824f5e5bd Mon Sep 17 00:00:00 2001
From: Shiji Yang <yangshiji66@outlook.com>
Date: Sun, 10 Aug 2025 18:11:01 +0800
Subject: [PATCH] arm64: dts: mediatek: mt7986: increase ATF reserved memory to
256 kiB
The latest Mediatek open-source Trusted Firmware-A project has
reserved 256 KiB for BL2 and BL31. It is better to increase the
reserved memory region in the Linux kernel to protect the data.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -76,9 +76,9 @@
record-size = <0x1000>;
};
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ /* 256 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */
secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
+ reg = <0 0x43000000 0 0x40000>;
no-map;
};

2
target/linux/mediatek/patches-6.12/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
View File

@@ -51,7 +51,7 @@ Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
&tphy->src_coef);
}
+ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
+ if (of_property_present(np, "mediatek,phy-switch")) {
+ tphy->hif = syscon_regmap_lookup_by_phandle(np,
+ "mediatek,phy-switch");
+ if (IS_ERR(tphy->hif)) {

133
target/linux/mediatek/patches-6.12/320-hwrng-add-driver-for-MediaTek-TRNG-SMC.patch
View File

@@ -1,133 +0,0 @@
From 9837930d6738e9fdc323ad887ace7c236a61d70c Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 25 Jan 2023 00:27:49 +0000
Subject: [PATCH] hwrng: add driver for MediaTek TRNG SMC
Add driver providing kernel-side support for the Random Number
Generator hardware found on Mediatek SoCs which have a driver in ARM
TrustedFirmware-A allowing Linux to read random numbers using a
non-standard vendor-defined Secure Monitor Call.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/char/hw_random/Kconfig | 16 +++++++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/mtk-rng-v2.c | 74 +++++++++++++++++++++++++++++
3 files changed, 91 insertions(+)
create mode 100644 drivers/char/hw_random/mtk-rng-v2.c
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -451,6 +451,23 @@ config HW_RANDOM_MTK
If unsure, say Y.
+config HW_RANDOM_MTK_V2
+ tristate "Mediatek Random Number Generator support (v2/SMC)"
+ depends on HAVE_ARM_SMCCC
+ depends on HW_RANDOM
+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+ default y
+ help
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on Mediatek SoCs which have a driver
+ in ARM TrustedFirmware-A allowing Linux to read using a non-
+ standard vendor-defined Secure Monitor Call.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mtk-rng-v2.
+
+ If unsure, say Y.
+
config HW_RANDOM_S390
tristate "S390 True Random Number Generator support"
depends on S390
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-r
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
obj-$(CONFIG_HW_RANDOM_MTK) += mtk-rng.o
+obj-$(CONFIG_HW_RANDOM_MTK_V2) += mtk-rng-v2.o
obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o
obj-$(CONFIG_HW_RANDOM_KEYSTONE) += ks-sa-rng.o
obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-rng.o
--- /dev/null
+++ b/drivers/char/hw_random/mtk-rng-v2.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Mediatek Hardware Random Number Generator (v2/SMCC)
+ *
+ * Copyright (C) 2023 Daniel Golle <daniel@makrotopia.org>
+ * based on patch from Mingming Su <Mingming.Su@mediatek.com>
+ */
+#define MTK_RNG_DEV KBUILD_MODNAME
+
+#include <linux/arm-smccc.h>
+#include <linux/err.h>
+#include <linux/hw_random.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
+
+#define MTK_SIP_KERNEL_GET_RND MTK_SIP_SMC_CMD(0x550)
+
+static int mtk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ struct arm_smccc_res res;
+ int retval = 0;
+
+ while (max >= sizeof(u32)) {
+ arm_smccc_smc(MTK_SIP_KERNEL_GET_RND, 0, 0, 0, 0, 0, 0, 0,
+ &res);
+ if (res.a0)
+ break;
+
+ *(u32 *)buf = res.a1;
+ retval += sizeof(u32);
+ buf += sizeof(u32);
+ max -= sizeof(u32);
+ }
+
+ return retval || !wait ? retval : -EIO;
+}
+
+static int mtk_rng_v2_probe(struct platform_device *pdev)
+{
+ struct hwrng *trng;
+
+ trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
+ if (!trng)
+ return -ENOMEM;
+
+ trng->name = pdev->name;
+ trng->read = mtk_rng_v2_read;
+ trng->quality = 900;
+
+ return devm_hwrng_register(&pdev->dev, trng);
+}
+
+static const struct of_device_id mtk_rng_v2_match[] = {
+ { .compatible = "mediatek,mt7981-rng" },
+ { .compatible = "mediatek,mt7987-rng" },
+ { .compatible = "mediatek,mt7988-rng" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_rng_v2_match);
+
+static struct platform_driver mtk_rng_v2_driver = {
+ .probe = mtk_rng_v2_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = mtk_rng_v2_match,
+ },
+};
+module_platform_driver(mtk_rng_v2_driver);
+
+MODULE_DESCRIPTION("Mediatek Random Number Generator Driver (v2/SMC)");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+MODULE_LICENSE("GPL");

212
target/linux/mediatek/patches-6.12/320-hwrng-mtk-add-support-for-hw-access-via-SMCC.patch Normal file
View File

@@ -0,0 +1,212 @@
From d211e2184d820207d14f5e8f84938c639875bf0d Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 3 Mar 2026 23:45:46 +0000
Subject: [PATCH] hwrng: mtk - add support for hw access via SMCC
Newer versions of ARM TrustedFirmware-A on MediaTek's ARMv8 SoCs no longer
allow accessing the TRNG from outside of the trusted firmware.
Instead, a vendor-defined custom Secure Monitor Call can be used to
acquire random bytes.
Add support for newer SoCs (MT7981, MT7987, MT7988). On MT7986 the best bet
is to test if firmware blocks direct access to the hwrng and if so, expect
the SMCC interface to be usable.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/char/hw_random/mtk-rng.c | 128 ++++++++++++++++++++++++++-----
1 file changed, 107 insertions(+), 21 deletions(-)
--- a/drivers/char/hw_random/mtk-rng.c
+++ b/drivers/char/hw_random/mtk-rng.c
@@ -3,6 +3,7 @@
* Driver for Mediatek Hardware Random Number Generator
*
* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
+ * Copyright (C) 2026 Daniel Golle <daniel@makrotopia.org>
*/
#define MTK_RNG_DEV KBUILD_MODNAME
@@ -17,6 +18,8 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/arm-smccc.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
/* Runtime PM autosuspend timeout: */
#define RNG_AUTOSUSPEND_TIMEOUT 100
@@ -30,6 +33,11 @@
#define RNG_DATA 0x08
+/* Driver feature flags */
+#define MTK_RNG_SMC BIT(0)
+
+#define MTK_SIP_KERNEL_GET_RND MTK_SIP_SMC_CMD(0x550)
+
#define to_mtk_rng(p) container_of(p, struct mtk_rng, rng)
struct mtk_rng {
@@ -37,6 +45,7 @@ struct mtk_rng {
struct clk *clk;
struct hwrng rng;
struct device *dev;
+ unsigned long flags;
};
static int mtk_rng_init(struct hwrng *rng)
@@ -104,6 +113,56 @@ static int mtk_rng_read(struct hwrng *rn
return retval || !wait ? retval : -EIO;
}
+static int mtk_rng_read_smc(struct hwrng *rng, void *buf, size_t max,
+ bool wait)
+{
+ struct arm_smccc_res res;
+ int retval = 0;
+
+ while (max >= sizeof(u32)) {
+ arm_smccc_smc(MTK_SIP_KERNEL_GET_RND, 0, 0, 0, 0, 0, 0, 0,
+ &res);
+ if (res.a0)
+ break;
+
+ *(u32 *)buf = res.a1;
+ retval += sizeof(u32);
+ buf += sizeof(u32);
+ max -= sizeof(u32);
+ }
+
+ return retval || !wait ? retval : -EIO;
+}
+
+static bool mtk_rng_hw_accessible(struct mtk_rng *priv)
+{
+ u32 val;
+ int err;
+
+ err = clk_prepare_enable(priv->clk);
+ if (err)
+ return false;
+
+ val = readl(priv->base + RNG_CTRL);
+ val |= RNG_EN;
+ writel(val, priv->base + RNG_CTRL);
+
+ val = readl(priv->base + RNG_CTRL);
+
+ if (val & RNG_EN) {
+ /* HW is accessible, clean up: disable RNG and clock */
+ writel(val & ~RNG_EN, priv->base + RNG_CTRL);
+ clk_disable_unprepare(priv->clk);
+ return true;
+ }
+
+ /*
+ * If TF-A blocks direct access, the register reads back as 0.
+ * Leave the clock enabled as TF-A's SMC handler needs it.
+ */
+ return false;
+}
+
static int mtk_rng_probe(struct platform_device *pdev)
{
int ret;
@@ -115,23 +174,42 @@ static int mtk_rng_probe(struct platform
priv->dev = &pdev->dev;
priv->rng.name = pdev->name;
-#ifndef CONFIG_PM
- priv->rng.init = mtk_rng_init;
- priv->rng.cleanup = mtk_rng_cleanup;
-#endif
- priv->rng.read = mtk_rng_read;
priv->rng.quality = 900;
+ priv->flags = (unsigned long)device_get_match_data(&pdev->dev);
- priv->clk = devm_clk_get(&pdev->dev, "rng");
- if (IS_ERR(priv->clk)) {
- ret = PTR_ERR(priv->clk);
- dev_err(&pdev->dev, "no clock for device: %d\n", ret);
- return ret;
+ if (!(priv->flags & MTK_RNG_SMC)) {
+ priv->clk = devm_clk_get(&pdev->dev, "rng");
+ if (IS_ERR(priv->clk)) {
+ ret = PTR_ERR(priv->clk);
+ dev_err(&pdev->dev, "no clock for device: %d\n", ret);
+ return ret;
+ }
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ if (IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) &&
+ of_device_is_compatible(pdev->dev.of_node,
+ "mediatek,mt7986-rng") &&
+ !mtk_rng_hw_accessible(priv)) {
+ priv->flags |= MTK_RNG_SMC;
+ dev_info(&pdev->dev,
+ "HW RNG not MMIO accessible, using SMC\n");
+ }
}
- priv->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ if (priv->flags & MTK_RNG_SMC) {
+ if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC))
+ return -ENODEV;
+ priv->rng.read = mtk_rng_read_smc;
+ } else {
+#ifndef CONFIG_PM
+ priv->rng.init = mtk_rng_init;
+ priv->rng.cleanup = mtk_rng_cleanup;
+#endif
+ priv->rng.read = mtk_rng_read;
+ }
ret = devm_hwrng_register(&pdev->dev, &priv->rng);
if (ret) {
@@ -140,12 +218,15 @@ static int mtk_rng_probe(struct platform
return ret;
}
- dev_set_drvdata(&pdev->dev, priv);
- pm_runtime_set_autosuspend_delay(&pdev->dev, RNG_AUTOSUSPEND_TIMEOUT);
- pm_runtime_use_autosuspend(&pdev->dev);
- ret = devm_pm_runtime_enable(&pdev->dev);
- if (ret)
- return ret;
+ if (!(priv->flags & MTK_RNG_SMC)) {
+ dev_set_drvdata(&pdev->dev, priv);
+ pm_runtime_set_autosuspend_delay(&pdev->dev,
+ RNG_AUTOSUSPEND_TIMEOUT);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ ret = devm_pm_runtime_enable(&pdev->dev);
+ if (ret)
+ return ret;
+ }
dev_info(&pdev->dev, "registered RNG driver\n");
@@ -182,8 +263,12 @@ static const struct dev_pm_ops mtk_rng_p
#endif /* CONFIG_PM */
static const struct of_device_id mtk_rng_match[] = {
- { .compatible = "mediatek,mt7986-rng" },
{ .compatible = "mediatek,mt7623-rng" },
+ { .compatible = "mediatek,mt7622-rng" },
+ { .compatible = "mediatek,mt7981-rng", .data = (void *)MTK_RNG_SMC },
+ { .compatible = "mediatek,mt7986-rng" },
+ { .compatible = "mediatek,mt7987-rng", .data = (void *)MTK_RNG_SMC },
+ { .compatible = "mediatek,mt7988-rng", .data = (void *)MTK_RNG_SMC },
{},
};
MODULE_DEVICE_TABLE(of, mtk_rng_match);
@@ -201,4 +286,5 @@ module_platform_driver(mtk_rng_driver);
MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
MODULE_LICENSE("GPL");

6
target/linux/mediatek/patches-6.12/330-snand-mtk-bmt-support.patch
View File

@@ -8,7 +8,7 @@
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
{
@@ -1529,6 +1530,7 @@ static int spinand_probe(struct spi_mem
@@ -1596,6 +1597,7 @@ static int spinand_probe(struct spi_mem
if (ret)
return ret;
@@ -16,7 +16,7 @@
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto err_spinand_cleanup;
@@ -1536,6 +1538,7 @@ static int spinand_probe(struct spi_mem
@@ -1603,6 +1605,7 @@ static int spinand_probe(struct spi_mem
return 0;
err_spinand_cleanup:
@@ -24,7 +24,7 @@
spinand_cleanup(spinand);
return ret;
@@ -1554,6 +1557,7 @@ static int spinand_remove(struct spi_mem
@@ -1621,6 +1624,7 @@ static int spinand_remove(struct spi_mem
if (ret)
return ret;

12
target/linux/mediatek/patches-6.12/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
View File

@@ -18,16 +18,16 @@ Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o foresee.o gigadevice.o
+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o foresee.o gigadevice.o
-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fmsh.o foresee.o gigadevice.o
+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o fmsh.o foresee.o gigadevice.o
spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1117,6 +1117,7 @@ static const struct spinand_manufacturer
&ato_spinand_manufacturer,
@@ -1181,6 +1181,7 @@ static const struct spinand_manufacturer
&esmt_c8_spinand_manufacturer,
&etron_spinand_manufacturer,
&fmsh_spinand_manufacturer,
+ &fidelix_spinand_manufacturer,
&foresee_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
@@ -113,10 +113,10 @@ Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -264,6 +264,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer ato_spinand_manufacturer;
@@ -266,6 +266,7 @@ extern const struct spinand_manufacturer
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
extern const struct spinand_manufacturer foresee_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;

2
target/linux/mediatek/patches-6.12/360-pinctrl-mediatek-add-mt7987-pinctrl-support.patch
View File

@@ -750,7 +750,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ .nfuncs = ARRAY_SIZE(mt7987_functions),
+ .eint_hw = &mt7987_eint_hw,
+ .gpio_m = 0,
+ .ies_present = false,
+ .ies_present = true,
+ .base_names = mt7987_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names),
+ .bias_disable_set = mtk_pinconf_bias_disable_set,

19
target/linux/mediatek/patches-6.12/411-mtd-spinand-fix-support-for-FORESEE.patch Normal file
View File

@@ -0,0 +1,19 @@
Force update_cache_variants to use reset for Foresee NAND with bad blocks
Tested on Xiaomi AX3000T + F35SQA001G with bad blocks and without bad blocks
Signed-off-by: Dim Fish <dimfish@gmail.com>
--- a/drivers/mtd/nand/spi/foresee.c
+++ b/drivers/mtd/nand/spi/foresee.c
@@ -22,8 +22,8 @@ static SPINAND_OP_VARIANTS(write_cache_v
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)

4
target/linux/mediatek/patches-6.12/433-drivers-spi-mem-Add-spi-calibration-hook.patch
View File

@@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -466,6 +466,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
@@ -486,6 +486,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
}
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
@@ -28,7 +28,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
* upper layer if necessary
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -372,6 +372,10 @@ bool spi_mem_supports_op(struct spi_mem
@@ -390,6 +390,10 @@ bool spi_mem_supports_op(struct spi_mem
int spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op);

4
target/linux/mediatek/patches-6.12/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
View File

@@ -11,7 +11,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1155,6 +1155,56 @@ static int spinand_manufacturer_match(st
@@ -1220,6 +1220,56 @@ static int spinand_manufacturer_match(st
return -EOPNOTSUPP;
}
@@ -68,7 +68,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
static int spinand_id_detect(struct spinand_device *spinand)
{
u8 *id = spinand->id.data;
@@ -1406,6 +1456,10 @@ static int spinand_init(struct spinand_d
@@ -1473,6 +1523,10 @@ static int spinand_init(struct spinand_d
if (!spinand->scratchbuf)
return -ENOMEM;

2
target/linux/mediatek/patches-6.12/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
View File

@@ -12,7 +12,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1196,7 +1196,10 @@ static int spinand_cal_read(void *priv,
@@ -1261,7 +1261,10 @@ static int spinand_cal_read(void *priv,
if (ret)
return ret;

4
target/linux/mediatek/patches-6.12/500-gsw-rtl8367s-mt7622-support.patch
View File

@@ -15,8 +15,8 @@
select CRC16
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -114,6 +114,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/
obj-y += rtl8261n/
@@ -113,6 +113,7 @@ obj-$(CONFIG_REALTEK_PHY) += realtek/
obj-$(CONFIG_REALTEK_PHY) += realtek/
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
+obj-$(CONFIG_RTL8367S_GSW) += rtk/

34
target/linux/mediatek/patches-6.12/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
View File

@@ -1,34 +0,0 @@
From: qizhong cheng <qizhong.cheng@mediatek.com>
Date: Mon, 27 Dec 2021 21:31:10 +0800
Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
stabilize
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.
Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
---
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -700,6 +700,13 @@ static int mtk_pcie_startup_port_v2(stru
*/
msleep(100);
+ /*
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
+ */
+ msleep(100);
+
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
val = readl(port->base + PCIE_RST_CTRL);
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |

2
target/linux/mediatek/patches-6.12/700-net-phy-mediatek-Add-2.5Gphy-firmware-dt-bindings-an.patch
View File

@@ -57,7 +57,7 @@ Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
+ };
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14426,9 +14426,10 @@ F: include/linux/pcs/pcs-mtk-usxgmii.h
@@ -14439,9 +14439,10 @@ F: include/linux/pcs/pcs-mtk-usxgmii.h
MEDIATEK ETHERNET PHY DRIVERS
M: Daniel Golle <daniel@makrotopia.org>
M: Qingfang Deng <dqfext@gmail.com>

6
target/linux/mediatek/patches-6.12/701-net-phy-mediatek-add-driver-for-built-in-2.5G-ethern.patch
View File

@@ -20,7 +20,7 @@ Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14430,6 +14430,7 @@ M: Sky Huang <SkyLake.Huang@mediatek.com
@@ -14443,6 +14443,7 @@ M: Sky Huang <SkyLake.Huang@mediatek.com
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/mediatek,2p5gphy-fw.yaml
@@ -61,7 +61,7 @@ Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/phy.h>
+#include <linux/pm_domain.h>
@@ -386,7 +386,7 @@ Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
+
+module_phy_driver(mtk_2p5gephy_driver);
+
+static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
+static const struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
+ { PHY_ID_MATCH_VENDOR(0x00339c00) },
+ { }
+};

2
target/linux/mediatek/patches-6.12/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
View File

@@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
struct mtk_pcie_port;
/**
@@ -1052,6 +1058,27 @@ static int mtk_pcie_setup(struct mtk_pci
@@ -1045,6 +1051,27 @@ static int mtk_pcie_setup(struct mtk_pci
struct mtk_pcie_port *port, *tmp;
int err, slot;

63
target/linux/mediatek/patches-6.12/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
View File

@@ -1,63 +0,0 @@
From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 6 Apr 2023 23:36:50 +0100
Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
MAC drivers using phylink expect SGMII in-band-status to be switched off
when attached to a PHY. Make sure this is the case also for mxl-gpy which
keeps SGMII in-band-status in case of SGMII interface mode is used.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
--- a/drivers/net/phy/mxl-gpy.c
+++ b/drivers/net/phy/mxl-gpy.c
@@ -380,8 +380,11 @@ static bool gpy_2500basex_chk(struct phy
phydev->speed = SPEED_2500;
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
- VSPEC1_SGMII_CTRL_ANEN, 0);
+
+ if (!phydev->phylink)
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+ VSPEC1_SGMII_CTRL_ANEN, 0);
+
return true;
}
@@ -432,6 +435,14 @@ static int gpy_config_aneg(struct phy_de
u32 adv;
int ret;
+ /* Disable SGMII auto-negotiation if using phylink */
+ if (phydev->phylink) {
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+ VSPEC1_SGMII_CTRL_ANEN, 0);
+ if (ret < 0)
+ return ret;
+ }
+
if (phydev->autoneg == AUTONEG_DISABLE) {
/* Configure half duplex with genphy_setup_forced,
* because genphy_c45_pma_setup_forced does not support.
@@ -554,6 +565,8 @@ static int gpy_update_interface(struct p
switch (phydev->speed) {
case SPEED_2500:
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ if (phydev->phylink)
+ break;
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
VSPEC1_SGMII_CTRL_ANEN, 0);
if (ret < 0) {
@@ -567,7 +580,7 @@ static int gpy_update_interface(struct p
case SPEED_100:
case SPEED_10:
phydev->interface = PHY_INTERFACE_MODE_SGMII;
- if (gpy_sgmii_aneg_en(phydev))
+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
break;
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
* if ANEG is disabled (in 2500-BaseX mode).

4
target/linux/mediatek/patches-6.12/737-net-dsa-add-Airoha-AN8855.patch
View File

@@ -216,10 +216,10 @@ Christian Marangi (9):
config NET_DSA_LANTIQ_GSWIP
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
ifdef CONFIG_NET_DSA_LOOP
@@ -6,6 +6,7 @@ ifdef CONFIG_NET_DSA_LOOP
obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdinfo.o
endif
obj-$(CONFIG_NET_DSA_KS8995) += ks8995.o
+obj-$(CONFIG_NET_DSA_AN8855) += an8855.o
obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o

1242
target/linux/mediatek/patches-6.12/739-net-add-negotiation-of-in-band-capabilities.patch
View File

File diff suppressed because it is too large Load Diff

10
target/linux/mediatek/patches-6.12/750-net-ethernet-mtk_eth_soc-add-mt7987-support.patch
View File

@@ -106,7 +106,7 @@ Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
mdelay(20);
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
@@ -2901,10 +2931,16 @@ static int mtk_tx_alloc(struct mtk_eth *
@@ -2908,10 +2938,16 @@ static int mtk_tx_alloc(struct mtk_eth *
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
val = MTK_QTX_SCH_MIN_RATE_EN |
@@ -126,7 +126,7 @@ Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
if (mtk_is_netsys_v1(eth))
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
@@ -5873,6 +5909,36 @@ static const struct mtk_soc_data mt7986_
@@ -5883,6 +5919,36 @@ static const struct mtk_soc_data mt7986_
},
};
@@ -144,14 +144,14 @@ Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
+ .has_accounting = true,
+ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ .tx = {
+ .desc_size = sizeof(struct mtk_tx_dma_v2),
+ DESC_SIZE(struct mtk_tx_dma_v2),
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ .dma_size = MTK_DMA_SIZE(2K),
+ .fq_dma_size = MTK_DMA_SIZE(4K),
+ },
+ .rx = {
+ .desc_size = sizeof(struct mtk_rx_dma_v2),
+ DESC_SIZE(struct mtk_rx_dma_v2),
+ .irq_done_mask = MTK_RX_DONE_INT_V2,
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
@@ -163,7 +163,7 @@ Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
static const struct mtk_soc_data mt7988_data = {
.reg_map = &mt7988_reg_map,
.ana_rgc3 = 0x128,
@@ -5934,6 +6000,7 @@ const struct of_device_id of_mtk_match[]
@@ -5944,6 +6010,7 @@ const struct of_device_id of_mtk_match[]
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },

2
target/linux/mediatek/patches-6.12/751-net-ethernet-mtk_eth_soc-revise-hardware-configuration-for-mt7987.patch
View File

@@ -15,7 +15,7 @@ Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4445,27 +4445,40 @@ static int mtk_hw_init(struct mtk_eth *e
@@ -4452,27 +4452,40 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);

2
target/linux/mediatek/patches-6.12/863-arm64-dts-mt7986-add-sound-wm8960.patch
View File

@@ -46,7 +46,7 @@ Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
};
&spi0 {
@@ -50,3 +80,13 @@
@@ -48,3 +78,13 @@
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

2
target/linux/mediatek/patches-6.12/901-arm-add-cmdline-override.patch
View File

@@ -37,7 +37,7 @@
* CONFIG_CMDLINE is meant to be a default in case nothing else
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2380,6 +2380,14 @@ config CMDLINE_FORCE
@@ -2381,6 +2381,14 @@ config CMDLINE_FORCE
endchoice

4
target/linux/mediatek/patches-6.12/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
View File

@@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
@@ -1333,6 +1333,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
@@ -47,7 +47,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
@@ -1349,6 +1367,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;

2
target/linux/mediatek/patches-6.12/950-smartrg-i2c-led-driver.patch
View File

@@ -29,6 +29,6 @@
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
+obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o
obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o
obj-$(CONFIG_LEDS_ST1202) += leds-st1202.o
obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o
obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o