Merge pull request #3710 from chipsalliance/dev

Update master with dev

src/main/scala/rocket/CSR.scala

@@ -913,7 +913,7 @@ class CSRFile(
       (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&
       (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))
     io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
-    io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
+    io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !usingVector.B
     io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
     io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
     io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')

src/main/scala/rocket/Configs.scala

@@ -8,6 +8,7 @@ import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
 import freechips.rocketchip.subsystem.{TilesLocated, NumTiles, HierarchicalLocation, RocketCrossingParams, SystemBusKey, CacheBlockBytes, RocketTileAttachParams, InSubsystem, InCluster, HierarchicalElementMasterPortParams, HierarchicalElementSlavePortParams, CBUS, CCBUS, ClustersLocated, TileAttachConfig, CloneTileAttachParams}
 import freechips.rocketchip.tile.{RocketTileParams, RocketTileBoundaryBufferParams, FPUParams}
+import freechips.rocketchip.util.{RationalDirection, Flexible}
 import scala.reflect.ClassTag
 
 // All the user-level bells and whistles
@@ -308,7 +309,7 @@ class WithCDC(crossingType: ClockCrossingType = SynchronousCrossing()) extends R
 class WithSeperateClockReset                                           extends RocketCrossingConfig(_.copy(forceSeparateClockReset = true))
 class WithSynchronousCDCs                                              extends WithCDC(SynchronousCrossing())
 class WithAsynchronousCDCs(depth: Int, sync: Int)                      extends WithCDC(AsynchronousCrossing(depth, sync))
-class WithRationalCDCs                                                 extends WithCDC(RationalCrossing())
+class WithRationalCDCs(direction: RationalDirection = Flexible)        extends WithCDC(RationalCrossing(direction))
 
 
 

src/main/scala/rocket/RVC.scala

@@ -155,12 +155,12 @@ class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
   }
 
   def q0_ill = {
-    def allz = !(x(12, 2).orR)
+    def immz = !(x(12, 5).orR)
     def fld = if (fLen >= 64) false.B else true.B
     def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
     def fsd = if (fLen >= 64) false.B else true.B
     def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
-    Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
+    Seq(immz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
   }
 
   def q1_ill = {

src/main/scala/rocket/RocketCore.scala

@@ -357,6 +357,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     val v_decode = rocketParams.vector.get.decoder(p)
     v_decode.io.inst := id_inst(0)
     v_decode.io.vconfig := csr.io.vector.get.vconfig
+    id_ctrl.vec := v_decode.io.vector
     when (v_decode.io.legal) {
       id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
       id_ctrl.fp := v_decode.io.fp
@@ -388,7 +389,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
     id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
     id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
-    (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
+    id_set_vconfig && csr.io.decode(0).vector_illegal ||
+    id_ctrl.vec && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
     id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
     ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
     id_raddr2_illegal && id_ctrl.rxs2 ||
@@ -1121,7 +1123,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
 
   io.fpu.valid := !ctrl_killd && id_ctrl.fp
   io.fpu.killx := ctrl_killx
-  io.fpu.killm := killm_common
+  io.fpu.killm := killm_common || vec_kill_mem
   io.fpu.inst := id_inst(0)
   io.fpu.fromint_data := ex_rs(0)
   io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu
@@ -1150,7 +1152,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     v.ex.rs2 := ex_rs(1)
     v.ex.pc := ex_reg_pc
     v.mem.frs1 := io.fpu.store_data
-    v.killm := killm_common
+    v.killm := killm_common || fpu_kill_mem
     v.status := csr.io.status
   }
 

src/main/scala/rocket/SimpleHellaCacheIF.scala

@@ -100,7 +100,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
   })
   io <> DontCare
 
-  val replayq = Module(new SimpleHellaCacheIFReplayQueue(2))
+  val replayq = Module(new SimpleHellaCacheIFReplayQueue(3))
   val req_arb = Module(new Arbiter(new HellaCacheReq, 2))
 
   val req_helper = DecoupledHelper(

src/main/scala/rocket/VectorUnit.scala

@@ -91,7 +91,8 @@ abstract class RocketVectorDecoder(implicit p: Parameters) extends CoreModule()(
   val io = IO(new Bundle {
     val inst = Input(UInt(32.W))
     val vconfig = Input(new VConfig)
-    val legal = Output(Bool())
+    val vector = Output(Bool()) // this is a vector instruction
+    val legal = Output(Bool()) // this is a legal vector instruction given vconfig
     val fp = Output(Bool())
     val read_rs1 = Output(Bool())
     val read_rs2 = Output(Bool())

src/main/scala/tile/FPU.scala

@@ -754,6 +754,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     val v_decode = v.decoder(p) // Only need to get ren1
     v_decode.io.inst := io.inst
     v_decode.io.vconfig := DontCare // core deals with this
+    v_decode.io.vconfig.vtype.vsew := io.v_sew
     when (v_decode.io.legal && v_decode.io.read_frs1) {
       id_ctrl.ren1 := true.B
       id_ctrl.swap12 := false.B
@@ -988,7 +989,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
     s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
   // Avoid structural hazards and nacking of external requests
   // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
-  io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
+  io.cp_req.ready := !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
 
   val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
   val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
@@ -1000,7 +1001,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
 
   val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
   io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
-  io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
+  io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight || mem_cp_valid)
   io.dec <> id_ctrl
   def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
   io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)

src/main/scala/tilelink/Xbar.scala

@@ -72,13 +72,13 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option
 
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
+    val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
+    override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
     if ((node.in.size * node.out.size) > (8*32)) {
       println (s"!!! WARNING !!!")
       println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
       println (s"!!! WARNING !!!")
     }
-    val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
-    override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
     TLXbar.circuit(policy, node.in, node.out)
   }
 }