issue #43: fix sorting sympy symbols by name

2026-05-31 00:15:16 +08:00 · 2026-04-30 15:35:27 +00:00
parent 29ffa6bb65
commit d6ef4f5fe4
6 changed files with 290 additions and 2 deletions
--- a/examples/freepdk45/characterize-flip-flop-slow.sh
+++ b/examples/freepdk45/characterize-flip-flop-slow.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+# SPDX-FileCopyrightText: 2026 Thomas Kramer, mbarlow
+#
+# SPDX-License-Identifier: CC0-1.0
+
+# Characterize a slow version of the DFFSR flip-flop (with set and reset).
+# See https://codeberg.org/librecell/lctime/issues/41
+
+NETLIST_DIR="../../test_data/freepdk45/netlists_pex"
+
+lctime --liberty template.lib \
+    --analyze-cell-function \
+    --include gpdk45nm.m \
+    --workingdir tmp \
+    --spice DFFSR_slow.pex.netlist \
+    --cell DFFSR \
+    --output-loads "0.05" \
+    --slew-times "0.1" \
+    --related-pin-transition "0.1" \
+    --debug \
+    --debug-plots \
+    --output dffsr.lib
+
--- a/examples/freepdk45/sdffx1_template.lib
+++ b/examples/freepdk45/sdffx1_template.lib
@@ -0,0 +1,139 @@
+/*
+ delay model :       typ
+ check model :       typ
+ power model :       typ
+ capacitance model : typ
+ other model :       typ
+*/
+library(gscl45nm) {
+
+  delay_model : table_lookup;
+  in_place_swap_mode : match_footprint;
+
+  /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit (1,pf);
+
+  slew_upper_threshold_pct_rise : 80;
+  slew_lower_threshold_pct_rise : 20;
+  slew_upper_threshold_pct_fall : 80;
+  slew_lower_threshold_pct_fall : 20;
+  input_threshold_pct_rise : 50;
+  input_threshold_pct_fall : 50;
+  output_threshold_pct_rise : 50;
+  output_threshold_pct_fall : 50;
+  nom_process : 1;
+  nom_voltage : 1.1;
+  nom_temperature : 27;
+  operating_conditions ( typical ) {
+     process : 1;
+     voltage : 1.1;
+     temperature : 27;
+  }
+  default_operating_conditions : typical;
+
+  lu_table_template(delay_template_4x5) {
+    variable_1 : total_output_net_capacitance;
+    variable_2 : input_net_transition;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
+  }
+  lu_table_template(delay_template_5x1) {
+    variable_1 : input_net_transition;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
+  }
+  lu_table_template(delay_template_6x1) {
+    variable_1 : input_net_transition;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(delay_template_6x6) {
+    variable_1 : total_output_net_capacitance;
+    variable_2 : input_net_transition;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  power_lut_template(energy_template_4x5) {
+    variable_1 : total_output_net_capacitance;
+    variable_2 : input_transition_time;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
+  }
+  power_lut_template(energy_template_6x6) {
+    variable_1 : total_output_net_capacitance;
+    variable_2 : input_transition_time;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(hold_template_3x6) {
+    variable_1 : related_pin_transition;
+    variable_2 : constrained_pin_transition;
+    index_1 ("1000.0, 1001.0, 1002.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  power_lut_template(passive_energy_template_5x1) {
+    variable_1 : input_transition_time;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
+  }
+  power_lut_template(passive_energy_template_6x1) {
+    variable_1 : input_transition_time;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(recovery_template_3x6) {
+    variable_1 : related_pin_transition;
+    variable_2 : constrained_pin_transition;
+    index_1 ("1000.0, 1001.0, 1002.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(recovery_template_6x6) {
+    variable_1 : related_pin_transition;
+    variable_2 : constrained_pin_transition;
+    index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(removal_template_3x6) {
+    variable_1 : related_pin_transition;
+    variable_2 : constrained_pin_transition;
+    index_1 ("1000.0, 1001.0, 1002.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+  lu_table_template(setup_template_3x6) {
+    variable_1 : related_pin_transition;
+    variable_2 : constrained_pin_transition;
+    index_1 ("1000.0, 1001.0, 1002.0");
+    index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0");
+  }
+
+
+cell (SDFFX1) {
+  ff (IQ,IQN) {
+    next_state : "(D * !SE) | (SDI * SE)";
+    clocked_on : "CLK";
+  }
+  pin(CLK)  {
+    direction : input;
+    clock : true;
+  }
+  pin(D)  {
+    direction : input;
+    nextstate_type : "data" ;
+  }
+  pin(SE)  {
+    direction : input;
+    nextstate_type : "scan_enable" ;
+  }
+  pin(SDI)  {
+    direction : input;
+    nextstate_type : "scan_in" ;
+  }
+  pin(Q)  {
+    direction : output;
+    function : "IQ";
+  }
+}
+
+
+}
--- a/src/lctime/characterization/flipflop.py
+++ b/src/lctime/characterization/flipflop.py
@@ -83,7 +83,7 @@ def characterize_flip_flop_output(
                       f"Take the first one ({preset_clear_input}).")

    # Find all data pins that are relevant for the internal state of the flip-flop.
-    data_in_pins = sorted(cell_type.next_state.atoms(sympy.Symbol))
+    data_in_pins = sorted(cell_type.next_state.atoms(sympy.Symbol), key=lambda n: n.name)
    logger.debug(f"Input pins relevant for internal state: {data_in_pins}")

    assert isinstance(cell_type.internal_state,
--- a/src/lctime/logic/seq_recognition.py
+++ b/src/lctime/logic/seq_recognition.py
@@ -529,7 +529,7 @@ def find_flipflop_state_control_and_observe_pins(
    assert isinstance(cell_type, SingleEdgeDFF), "cell_type must be a SingleEdgeDFF"
    
    # Find all data pins that are relevant for the internal state of the flip-flop.
-    data_in_pins = sorted(cell_type.next_state.atoms(sympy.Symbol))
+    data_in_pins = sorted(cell_type.next_state.atoms(sympy.Symbol), key=lambda n: n.name)
    logger.debug(f"Input pins relevant for internal state: {data_in_pins}")

    # Find data input pins which can control the output pin.
--- a/test_data/freepdk45/netlists_pex/DFFSR_slow.pex.netlist
+++ b/test_data/freepdk45/netlists_pex/DFFSR_slow.pex.netlist
@@ -0,0 +1,74 @@
+* File: DFFSR.pex.netlist
+* Created: Wed Jan  2 18:39:27 2008
+* Program "Calibre xRC"
+* Version "v2007.2_34.24"
+* 
+.subckt DFFSR  CLK D S R VDD GND Q
+* 
+MM32 GND Q_INT QP GND NMOS_VTL L=5e-08 W=2.5e-07
+MM33 VDD Q_INT QP VDD PMOS_VTL L=5e-08 W=5e-07
+MM34 GND QP Q GND NMOS_VTL L=5e-08 W=2.5e-07
+MM35 VDD QP Q VDD PMOS_VTL L=5e-08 W=5e-07
+* These 2 capacitors will extend CLK->Q to >900ps
+*C10  Q_INT GND 140f
+*C12  QP    GND 140f
+MM36 GND CLK CLKS1 GND NMOS_VTL L=5e-08 W=2.5e-07
+MM37 VDD CLK CLKS1 VDD PMOS_VTL L=5e-08 W=5e-07
+MM38 GND CLKS1 CLKS2 GND NMOS_VTL L=5e-08 W=2.5e-07
+MM39 VDD CLKS1 CLKS2 VDD PMOS_VTL L=5e-08 W=5e-07
+* These two capacitors should push the minimum clock time out to over 800ps
+C11  CLKS2    GND 140f
+C13  CLKS1    GND 140f
+MM24 a_47_71# CLKS2 GND GND NMOS_VTL L=5e-08 W=2.5e-07
+MM22 GND D a_57_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM23 GND a_47_71# a_47_4# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM21 a_57_6# a_47_71# a_23_27# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM20 a_23_27# a_47_4# a_2_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM16 a_10_6# R a_2_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM17 GND a_10_61# a_10_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM18 a_26_6# a_23_27# GND GND NMOS_VTL L=5e-08 W=5e-07
+MM19 a_10_61# S a_26_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM25 a_105_6# a_47_4# a_10_61# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM26 a_113_6# a_47_71# a_105_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM30 a_113_6# S a_146_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM29 a_146_6# a_122_6# GND GND NMOS_VTL L=5e-08 W=5e-07
+MM28 GND R a_130_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM27 a_130_6# a_105_6# a_122_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM31 GND a_122_6# Q_INT GND NMOS_VTL L=5e-08 W=2.5e-07
+MM8 a_47_71# CLKS2 VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM6 VDD D a_57_6# VDD PMOS_VTL L=5e-08 W=5e-07
+MM5 a_57_6# a_47_4# a_23_27# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM4 a_23_27# a_47_71# a_2_6# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM7 VDD a_47_71# a_47_4# VDD PMOS_VTL L=5e-08 W=5e-07
+MM0 a_2_6# R VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM1 VDD a_10_61# a_2_6# VDD PMOS_VTL L=5e-08 W=5e-07
+MM3 VDD S a_10_61# VDD PMOS_VTL L=5e-08 W=5e-07
+MM9 a_105_6# a_47_71# a_10_61# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM2 a_10_61# a_23_27# VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM10 a_113_6# a_47_4# a_105_6# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM13 a_113_6# a_122_6# VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM14 VDD S a_113_6# VDD PMOS_VTL L=5e-08 W=5e-07
+MM12 VDD R a_122_6# VDD PMOS_VTL L=5e-08 W=5e-07
+MM11 a_122_6# a_105_6# VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM15 VDD a_122_6# Q_INT VDD PMOS_VTL L=5e-08 W=5e-07
+c_14 a_47_4# 0 0.334871f
+c_29 a_47_71# 0 0.432635f
+c_35 CLK 0 0.0727998f
+c_42 D 0 0.0595369f
+c_48 a_57_6# 0 0.0164343f
+c_56 a_2_6# 0 0.0323757f
+c_67 a_23_27# 0 0.233891f
+c_77 a_10_61# 0 0.142227f
+c_88 S 0 0.207309f
+c_96 a_113_6# 0 0.0349704f
+c_108 R 0 0.213407f
+c_119 a_105_6# 0 0.163683f
+c_130 a_122_6# 0 0.396211f
+c_142 VDD 0 0.371445f
+c_155 GND 0 0.305932f
+c_160 Q_INT 0 0.0656414f
+*
+*
+.ends
+*
+*
--- a/test_data/freepdk45/netlists_pex/SDFFX1.netlist
+++ b/test_data/freepdk45/netlists_pex/SDFFX1.netlist
@@ -0,0 +1,51 @@
+* File: DFFPOSX1.pex.netlist
+* Created: Wed Jan  2 18:36:24 2008
+* Program "Calibre xRC"
+* Version "v2007.2_34.24"
+* 
+.subckt SDFFX1  CLK Q D SDI SE GND VDD
+* 
+MM21 Q a_66_6# GND GND NMOS_VTL L=5e-08 W=5e-07
+MM19 a_76_6# a_2_6# a_66_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM20 GND Q a_76_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM18 a_66_6# CLK a_61_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM17 a_61_6# a_34_4# GND GND NMOS_VTL L=5e-08 W=2.5e-07
+MM10 GND CLK a_2_6# GND NMOS_VTL L=5e-08 W=5e-07
+MM16 a_34_4# a_22_6# GND GND NMOS_VTL L=5e-08 W=2.5e-07
+MM15 GND a_34_4# a_31_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM14 a_31_6# CLK a_22_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM13 a_22_6# a_2_6# a_17_6# GND NMOS_VTL L=5e-08 W=2.5e-07
+MM12 a_17_6# DINT GND GND NMOS_VTL L=5e-08 W=2.5e-07
+MM11 Q a_66_6# VDD VDD PMOS_VTL L=5e-08 W=1e-06
+MM9 VDD Q a_76_84# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM8 a_76_84# CLK a_66_6# VDD PMOS_VTL L=5e-08 W=2.5e-07
+MM7 a_66_6# a_2_6# a_61_74# VDD PMOS_VTL L=5e-08 W=5e-07
+MM6 a_61_74# a_34_4# VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM0 VDD CLK a_2_6# VDD PMOS_VTL L=5e-08 W=1e-06
+MM5 a_34_4# a_22_6# VDD VDD PMOS_VTL L=5e-08 W=5e-07
+MM4 VDD a_34_4# a_31_74# VDD PMOS_VTL L=5e-08 W=5e-07
+MM3 a_31_74# a_2_6# a_22_6# VDD PMOS_VTL L=5e-08 W=5e-07
+MM2 a_22_6# CLK a_17_74# VDD PMOS_VTL L=5e-08 W=5e-07
+MM1 a_17_74# DINT VDD VDD PMOS_VTL L=5e-08 W=5e-07
+* MUX
+MM35 GND SE SEB GND NMOS_VTL L=5e-08 W=2.5e-07
+MM30 VDD SE SEB VDD PMOS_VTL L=5e-08 W=5e-07
+
+MM39 GND D n2 GND NMOS_VTL L=5e-08 W=5e-07
+MM38 n2 SEB DINTB GND NMOS_VTL L=5e-08 W=5e-07
+
+MM37 DINTB SE n3 GND NMOS_VTL L=5e-08 W=5e-07
+MM36 n3 SDI GND GND NMOS_VTL L=5e-08 W=5e-07
+
+MM34 VDD D n4 VDD PMOS_VTL L=5e-08 W=1e-06
+MM33 n4 SE DINTB VDD PMOS_VTL L=5e-08 W=1e-06
+
+MM32 DINTB SEB n5 VDD PMOS_VTL L=5e-08 W=1e-06
+MM31 n5 SDI VDD VDD PMOS_VTL L=5e-08 W=1e-06
+
+MM45 GND DINTB DINT GND NMOS_VTL L=5e-08 W=2.5e-07
+MM40 VDD DINTB DINT VDD PMOS_VTL L=5e-08 W=5e-07
+*
+*
+.ends
+*