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6a96a7471b · Merge pull request #2533 from lnis-uofu/patch_update · Updated 2026-05-24 11:44:01 +08:00

Branches

5f90ce02a6 · Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_flat_router_strong · Updated 2026-05-24 13:29:26 +08:00

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e252afeb1a · Merge branch 'master' into gg_custom_rrgraph_gen · Updated 2026-05-23 05:22:45 +08:00

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d4b229720a · Updated VPR architecture · Updated 2026-05-15 02:31:00 +08:00

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2adfaef7c0 · [core] typo · Updated 2026-05-13 08:57:55 +08:00

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a6e1a5cfc2 · Updating documentation · Updated 2026-05-03 10:25:27 +08:00

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1346e33832 · Adding single input gate in flat routing test · Updated 2026-04-25 12:29:54 +08:00

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6be228a282 · Print each cluster name in report_cluster_template instead of total count · Updated 2026-04-20 03:25:33 +08:00

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3befbafd5f · Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into marking_wired_luts · Updated 2026-04-08 06:37:20 +08:00

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7d15ee5176 · Addressed comments · Updated 2026-03-19 00:58:08 +08:00

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fa46f4e355 · Merge branch 'master' into gg_reorder_bitstream · Updated 2026-03-11 21:07:24 +08:00

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5c517bb328 · Merge branch 'master' into jr_pcf_patch · Updated 2026-02-25 13:58:13 +08:00

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ac6bd187ea · Merge branch 'master' into ql_custom_fabric_bitstream · Updated 2026-02-08 20:03:57 +08:00

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6044ea49ad · Merge branch 'master' into xt_pcf2sdc_hotfix · Updated 2026-01-31 05:40:53 +08:00

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7982d857b1 · uncomment assertions · Updated 2026-01-15 06:58:49 +08:00

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52ba4fb021 · Revert "Bump vtr-verilog-to-routing from d3c57bc to f19f9bb (#2312)" · Updated 2026-01-15 03:44:55 +08:00

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a42e51a0e1 · Bump vtr-verilog-to-routing from d3c57bc to f19f9bb · Updated 2026-01-13 16:03:10 +08:00

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dfc83263c7 · update_vtr · Updated 2025-12-25 03:54:16 +08:00

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5c17116b13 · [vtr] update version · Updated 2025-12-24 23:08:43 +08:00

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f3f42afa28 · [test] update pcf config command · Updated 2025-12-16 08:03:04 +08:00

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85ac643016 · [core] debug · Updated 2025-12-03 09:28:26 +08:00

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