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Fix typo in clock routing layer variables (#703)

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* Fix typo in clock routing layer variables

* Expose max_wire_length option for the repiar_clock_nets command
This commit is contained in:
Manar
2021-11-12 06:54:55 -06:00
committed by GitHub
parent 8950f1aaeb
commit 665626bb1f
5 changed files with 9 additions and 5 deletions
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3
configuration/README.md
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@@ -147,6 +147,7 @@ These variables are optional that can be specified in the design configuration f
| `CTS_SINK_CLUSTERING_SIZE` | Specifies the maximum number of sinks per cluster. <br> (Default: `25`) |
| `CTS_SINK_CLUSTERING_MAX_DIAMETER` | Specifies maximum diameter (in micron) of sink cluster. <br> (Default: `50`) |
| `CTS_REPORT_TIMING` | Specifies whether or not to run STA after clock tree synthesis using OpenROAD's estimate_parasitics -placement and generates reports under `logs/cts`. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
| `CTS_CLK_MAX_WIRE_LENGTH` | Specifies the maximum wire length on the clock net. Value in microns. <br> (Default: `0`) |
| `LIB_CTS` | The liberty file used for CTS. By default, this is the `LIB_SYNTH_COMPLETE` minus the cells with drc errors as specified by the drc exclude list. <br> (Default: `$::env(TMP_DIR)/cts.lib`) |
### Routing
@@ -155,6 +156,8 @@ These variables are optional that can be specified in the design configuration f
|---------------|---------------------------------------------------------------|
| `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
| `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
| `GLB_RT_CLOCK_MINLAYER` | The number of lowest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MINLAYER`)|
| `GLB_RT_CLOCK_MAXLAYER` | The number of highest layer to be used in routing the clock net. <br> (Default: `GLB_RT_MAXLAYER`)|
| `GLB_RT_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph. Values range from 0 to 1. <br> 1 = most reduction, 0 = least reduction <br> (Default: `0`)|
| `GLB_RT_L1_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to li1 layer in sky130A. Values range from 0 to 1 <br> (Default: `0.99`) |
| `GLB_RT_L2_ADJUSTMENT` | Reduction in the routing capacity of the edges between the cells in the global routing graph but specific to met1 in sky130A. Values range from 0 to 1 <br> (Default: `0`) |

1
configuration/cts.tcl
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@@ -19,3 +19,4 @@ set ::env(CTS_TOLERANCE) 100
set ::env(CTS_SINK_CLUSTERING_SIZE) 25
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 50
set ::env(CTS_REPORT_TIMING) 1
set ::env(CTS_CLK_MAX_WIRE_LENGTH) 0

2
scripts/openroad/cts.tcl
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@@ -67,7 +67,7 @@ set_propagated_clock [all_clocks]
estimate_parasitics -placement
puts "\[INFO]: Repairing long wires on clock nets..."
# CTS leaves a long wire from the pad to the clock tree root.
repair_clock_nets
repair_clock_nets -max_wire_length $::env(CTS_CLK_MAX_WIRE_LENGTH)
estimate_parasitics -placement
write_def $::env(SAVE_DEF)

4
scripts/openroad/groute.tcl
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@@ -39,13 +39,13 @@ if { $::env(DIODE_INSERTION_STRATEGY) == 3 } {
set signal_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MINLAYER)-1}]]
set signal_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MAXLAYER)-1}]]
if { ![info exists ::env(CLB_RT_CLOCK_MIN_LAYER)] } {
if { ![info exists ::env(GLB_RT_CLOCK_MINLAYER)] } {
set clock_min_layer $signal_min_layer
} else {
set clock_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MINLAYER)-1}]]
}
if { ![info exists ::env(CLB_RT_CLOCK_MAX_LAYER)] } {
if { ![info exists ::env(GLB_RT_CLOCK_MAXLAYER)] } {
set clock_max_layer $signal_max_layer
} else {
set clock_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MAXLAYER)-1}]]

4
scripts/openroad/resizer_routing_timing.tcl
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@@ -41,13 +41,13 @@ if { [info exists ::env(DONT_USE_CELLS)] } {
set signal_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MINLAYER)-1}]]
set signal_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_MAXLAYER)-1}]]
if { ![info exists ::env(CLB_RT_CLOCK_MIN_LAYER)] } {
if { ![info exists ::env(GLB_RT_CLOCK_MINLAYER)] } {
set clock_min_layer $signal_min_layer
} else {
set clock_min_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MINLAYER)-1}]]
}
if { ![info exists ::env(CLB_RT_CLOCK_MAX_LAYER)] } {
if { ![info exists ::env(GLB_RT_CLOCK_MAXLAYER)] } {
set clock_max_layer $signal_max_layer
} else {
set clock_max_layer [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(GLB_RT_CLOCK_MAXLAYER)-1}]]