~ use tclmodules (`.tm`) files instead of pkgIndex.tcl for openlane and openlane_utils
~ change tagging to use the version from the `.tm` files instead of the day of the release
~ include superstable branch in tagging efforts (even though this doesn't mean much in `master`…)
~ Increases banner size for OpenLane 2, now uses a PNG rendered at 1200 API on macOS for consistency
~ Updated Flow Architecture Document
Co-authored-by: Mohamed Gaber <donn@efabless.com>
+ Repository is now a Nix flake
~ Change all invocations of `openroad -python` to use `run_odbpy_script` for consistency
~ Change build system from ad-hoc to Nix, still producing a Docker image as a final result
~ Update KLayout scripts to use `klayout-pymod` or properly parse commandline arguments
~ `open_pdks` -> `bdc9412` to match OpenLane 2
- Remove local installer; `nix run .` will run OpenLane natively
I worked on adding documentation to OpenLane in Spanish using a more visually appealing website, and providing a translation of the openlane configuration parameters.
I only updating the link, the website used to come from "erickcb", my personal github account, but it is now from "lima-ucr", the account for the laboratory I run at Universidad de Costa Rica
Signed-off-by: Laboratorio de Investigación en Microelectrónica y Arquitectura de Computadoras, EIE -- UCR <135917299+lima-ucr@users.noreply.github.com>
~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)
+ Add tt05-i2c-bert (https://github.com/dlmiles/tt05-i2c-bert) to CI
~ Replace instances of ABC command `rewrite` with `drw -l` with `SYNTH_ABC_LEGACY_REWRITE` being set to `1` restoring the older functionality (`0` by default)
~ Replace instances of ABC command `refactor` with `drf -l` with `SYNTH_ABC_LEGACY_REFACTOR` being set to `1` restoring the older functionality (`0` by default)
~ Added `delete t:\$print` to `synth.tcl` to fix designs such as PPU with synthesized prints (as in https://github.com/efabless/openlane2/pull/189)
---------
Co-authored-by: Mohamed Gaber <donn@efabless.com>
~ Set default `FP_IO_MODE` to 0.
~ Better `FP_IO_MODE` documentation.
~ Change the behavior of `FP_IO_MODE` 0:
1. Run global placement with `-skip_io` flag.
2. Run io placement (again).
3. Run global placement.
If `FP_IO_MODE` is 1, steps 1 and 2 are skipped.
~ Change tcl functions `global_placement_or` and `place_io` to allow for the changes mentioned above.
- Remove `cvc_rv` utility (upstream no longer willing to support it as part of the flow)
~ Fix bug with OpenLane docker image builder copying run folders
+ Add PNR_SDC_FILE
+ Warn when (PNR|SIGNOFF)_SDC_FILE are not overwritten by the user.
+ Add SDC_IN and DEFAULT_SDC_FILE to ignore list in CI
+ Add per corner max slew/fanout/cap count to sta report
+ Add per corner worst hold and setup value to sta report
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Always use PNR_SDC_FILE instead of CURRENT_SDC except during signoff stage, where SIGNOFF_SDC_FILE is used instead
~ Enable DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION for APU which fails after SDC updates.
~ Adjust timing checkers according to the new reported values
+ Warn when IMPLEMENTATION_SDC_FILE is not overwritten by the user.
+ Add SDC_IN and IMPLEMENTATION_SDC_FILE_DEFAULT to ignore list in ci Check Variables flow
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Rename BASE_SDC_FILE to IMPLEMENTATION_SDC_FILE.
~ Always use IMPLMEMENTATION_SDC_FILE instead of CURRENT_SDC except during signoff stage
+ Added `make docs` target to primary Makefile to generate documentation
~ Update documentation dependencies
~ Updated `tcl.py` to handle JSON lists of elements including whitespace by joining them with a comma (unless one of the elements already contains a comma), resolving odd JSON syntax
~ Re-organized and re-order configuration variables and edited descriptions for general consistency as well as adding anchors
~ Update all documentation dependencies
~ Fixed a number of broken links
- Remove dependency on `docutils` and `sphinx-autobuild` (both unused)
- Remove two of the custom documentation extensions
~ Move test designs to a separate repository and add it as a submodule.
~ Adjust test set to refer to designs in submodule.
~ Change design_dir in `run_tests.py` for artifact upload in the CI.
~ Fix fail condition on design name mismatch in `compare_regression_reports.py`
~ Print a better error message for design name mismatch mentioned previously.
~ Change regression benchmark to point reflect submodule change.
~ Change documentation to reflect new paths of designs.
+ Add aes_user_project_wrapper to ci designs to test EXTRA_SPEFS.
+ Add a step in CI workflow to replace `/` with `_` in design name for artifact upload.
~ Classified PDK variables by user modifiability
~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT`
~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT`
~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD`
- Removed `DEFAULT_MAX_TRAN` from PDK (unused)
Script uses regular expressions to create a set of documents variables and a set of used variables and compare them against each other. Some variables are internal, unexposed and others. These variables are whitelisted. See https://github.com/The-OpenROAD-Project/OpenLane/issues/1889
\+ Add documentation for `QUIT_ON_XOR_ERROR`
~ Rename `antenna.log` to `arc.log` and `magic_antenna.log` to avoid confusion
~ Separate PDK porting instructions and PDK variables
~ Add deprecated variables to documentation
~ Make existing deprecated variable documentation formatting-consistent and with replacement instructions
- Remove defaults from deprecated variables (they don't have any)
- Remove `LIB_MIN`/`LIB_MAX`: enough time has passed and PDK variables are annoying to deprecate
Co-authored-by: Donn <me@donn.website>
~ generalize verilator variables:
QUIT_ON_VERILATOR_ERRORS -> QUIT_ON_LINTER_ERRORS
QUIT_ON_VERILATOR_WARNINGS -> QUIT_ON_LINTER_WARNINGS
VERILATOR_RELATIVE_INCLUDES -> LINTER_RELATIVE_INCLUDES
RUN_VERILATOR -> RUN_LINTER
+ add LINTER_INCLUDE_PDK_MODELS
+ add LINTER_DEFINES
+ include verilator in ci tool updater
- do not include pdk verilog models using -I
- remove workaround for verilator std error
- disallow timing constructs. Print an error to the user to remove or guard them.
~ default to lef/def in order to generate lef with pin direction (and much faster than gds)
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation
\+ Add `gui.py`. Adding the help message here:
```
Usage: gui.py [OPTIONS] RUN_DIR
View specified layout from run_dir using supported viewers
Options:
--viewer [klayout|openroad] Viewer option [default: openroad]
-f, --format [def|odb|gds] Layout format to view [default: odb]
-s, --stage [cts|floorplan|placement|routing|signoff]
Optionally specify which stage to view
--help Show this message and exit.
```
\+ Mount HOME directory when running `make mount`.
\+ Add `-congestion_report_file` to steps that call global routing
+ Add `SYNTH_MAX_TRAN` to `base.sdc` (if set)
~ Fix syntax error in `all.tcl`
- Removed attempt(s) to calculate a default value for `SYNTH_MAX_TRAN` in `all.tcl`, `openroad/cts.tcl` and `yosys/synth.tcl`
+ add `RSZ_MULTICORNER_LIB`: a flag to read multicorner libs during resizer optimizations
+ add `RSZ_LIB_FASTEST`: defaults to `LIB_FASTEST`
+ add `RSZ_LIB_SLOWEST`: defaults to `LIB_SLOWEST`
+ add `LIB_CTS_SLOWEST`
+ add `LIB_CTS_FASTEST`
+ add `CTS_MULTICONER_LIB`
~ in `read_libs`, in `scripts/openroad/common/io.tcl`, iterate over each each corner definition to allow for reading multiple files for each corner.
~ replace `-override_libs` and `-multi_corner_libs` by `-lib_fastest`, `-lib_slowest` and `-lib_typical` and modify resizer and cts tcl scripts accordingly
~ don't make copies of files in `LIB_SYNTH_COMPLETE` for `RSZ_LIB`, instead point to the original files
+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD
~ Add reports for timing multi-corner STA across all process corners
~ Sort min/max report outputs by slack
~ Combine Slew, Fanout, Capacitance and Annotation Checks into one `_sta.checks.rpt`
~ Combine TNS, WNS, Worst_Slack into one `_sta.summary.rpt`
~ Fix regression in #1675 where logs were renamed and reports were not getting generated for some steps
~ Update documentation
\- Remove UMich ECO timing report vestiges
---
Based on feedback from @shalan, Fixes#875
~ set min distance in cfg file instead of using `FP_IO_MIN_DISTANCE`
~ don't quit when min distance < legal min distance and use legal min distance. by definition if min distance is illegal it is "minimum" and we can use a higher value
~ `min_distance` is not min spacing - adjust legal tracks in `io_place.py` under that assumption
+ add wrapper.tcl to capture magic errors ported from openlane2
~ use lef/def or gds instead of mag to write a lef through MAGIC_LEF_WRITE_USE_GDS
~ print lef write log file path
Fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1701
\~ Move Yosys check quitting entirely to Python script
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
\+ Add `SYNTH_CHECKS_ALLOW_TRISTATE` that allows tristate buffers in yosys `check`
\~ Fix wrong default value of `RUN_HEURISTIC_DIODE_INSERTION` in documentation
\~ Move Yosys check quitting entirely to Python script, can ignore tristate buffer-related warnings
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
