~ use tclmodules (`.tm`) files instead of pkgIndex.tcl for openlane and openlane_utils
~ change tagging to use the version from the `.tm` files instead of the day of the release
~ bump github action versions
- Remove `unset_propagated_clock` from:
1- `scripts/openroad/floorplan.tcl`
2- `scripts/openroad/resizer.tcl`
3- `scripts/openroad/sta/multi_corner.tcl`
To avoid using a generated SDC that doesn't include `set_propagated_clock` in signoff STA
~ Move test designs to a separate repository and add it as a submodule.
~ Adjust test set to refer to designs in submodule.
~ Change design_dir in `run_tests.py` for artifact upload in the CI.
~ Fix fail condition on design name mismatch in `compare_regression_reports.py`
~ Print a better error message for design name mismatch mentioned previously.
~ Change regression benchmark to point reflect submodule change.
~ Change documentation to reflect new paths of designs.
+ Add aes_user_project_wrapper to ci designs to test EXTRA_SPEFS.
+ Add a step in CI workflow to replace `/` with `_` in design name for artifact upload.
~ Classified PDK variables by user modifiability
~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT`
~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT`
~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD`
- Removed `DEFAULT_MAX_TRAN` from PDK (unused)
Script uses regular expressions to create a set of documents variables and a set of used variables and compare them against each other. Some variables are internal, unexposed and others. These variables are whitelisted. See https://github.com/The-OpenROAD-Project/OpenLane/issues/1889
\+ Add documentation for `QUIT_ON_XOR_ERROR`
* add more information to antenna violations report:
+ required ratio
+ partial ratio
+ violating pin
+ violating net
+ metal layer
* add --plain-out to print a list of violating pins
---------
Co-authored-by: Donn <me@donn.website>
~ Rename `antenna.log` to `arc.log` and `magic_antenna.log` to avoid confusion
~ Separate PDK porting instructions and PDK variables
~ Add deprecated variables to documentation
~ Make existing deprecated variable documentation formatting-consistent and with replacement instructions
- Remove defaults from deprecated variables (they don't have any)
- Remove `LIB_MIN`/`LIB_MAX`: enough time has passed and PDK variables are annoying to deprecate
Co-authored-by: Donn <me@donn.website>
An exit code of 2 is bypassed. It seems that an exit code that is not 2 is a failure of the python script itself not OpenLane flow. This exception is raised and propagated to the CI. However an exit code of 2 should be propagated as well after a reproducible is made. The CI flow shouldn't attempt to run benchmark when the flow failed.
~ generalize verilator variables:
QUIT_ON_VERILATOR_ERRORS -> QUIT_ON_LINTER_ERRORS
QUIT_ON_VERILATOR_WARNINGS -> QUIT_ON_LINTER_WARNINGS
VERILATOR_RELATIVE_INCLUDES -> LINTER_RELATIVE_INCLUDES
RUN_VERILATOR -> RUN_LINTER
+ add LINTER_INCLUDE_PDK_MODELS
+ add LINTER_DEFINES
+ include verilator in ci tool updater
- do not include pdk verilog models using -I
- remove workaround for verilator std error
- disallow timing constructs. Print an error to the user to remove or guard them.
add -hierarchical to get_cells: Searches hierarchy levels below the current instance for matches.
use get_property full_name instead get_property name to get the full
hierarchical name of a module
~ default to lef/def in order to generate lef with pin direction (and much faster than gds)
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation
`-gui` is superseded by `gui.py`. `or_gui` should still work for interactive scripts.
Dropping support for continuing existing runs. Users need to use `-overwrite` or provide a different tag.
the whole point of the powered def is to compare the power connections
of the rtl with the power connections defined in macro hooks. the
current implementation writes a def file generated from a netlist
created from the rtl and the final def generated after routing. this is
done in a python script followed by a tcl call to `write_verilog`
because there isn't a python api for writing verilog. this introduced a
problem where during `write_verilog` global connections defined in macro
hooks are set overwriting whatever changes to the power connections made in
the powered def. this pr add -no_global_connect during the
`write_verilog` step to avoid the override mentioned earlier.
\+ Add `gui.py`. Adding the help message here:
```
Usage: gui.py [OPTIONS] RUN_DIR
View specified layout from run_dir using supported viewers
Options:
--viewer [klayout|openroad] Viewer option [default: openroad]
-f, --format [def|odb|gds] Layout format to view [default: odb]
-s, --stage [cts|floorplan|placement|routing|signoff]
Optionally specify which stage to view
--help Show this message and exit.
```
\+ Mount HOME directory when running `make mount`.
\+ Add `-congestion_report_file` to steps that call global routing
+ Add `SYNTH_MAX_TRAN` to `base.sdc` (if set)
~ Fix syntax error in `all.tcl`
- Removed attempt(s) to calculate a default value for `SYNTH_MAX_TRAN` in `all.tcl`, `openroad/cts.tcl` and `yosys/synth.tcl`
+ add `RSZ_MULTICORNER_LIB`: a flag to read multicorner libs during resizer optimizations
+ add `RSZ_LIB_FASTEST`: defaults to `LIB_FASTEST`
+ add `RSZ_LIB_SLOWEST`: defaults to `LIB_SLOWEST`
+ add `LIB_CTS_SLOWEST`
+ add `LIB_CTS_FASTEST`
+ add `CTS_MULTICONER_LIB`
~ in `read_libs`, in `scripts/openroad/common/io.tcl`, iterate over each each corner definition to allow for reading multiple files for each corner.
~ replace `-override_libs` and `-multi_corner_libs` by `-lib_fastest`, `-lib_slowest` and `-lib_typical` and modify resizer and cts tcl scripts accordingly
~ don't make copies of files in `LIB_SYNTH_COMPLETE` for `RSZ_LIB`, instead point to the original files
