~ Rename `antenna.log` to `arc.log` and `magic_antenna.log` to avoid confusion
~ Separate PDK porting instructions and PDK variables
~ Add deprecated variables to documentation
~ Make existing deprecated variable documentation formatting-consistent and with replacement instructions
- Remove defaults from deprecated variables (they don't have any)
- Remove `LIB_MIN`/`LIB_MAX`: enough time has passed and PDK variables are annoying to deprecate
Co-authored-by: Donn <me@donn.website>
~ generalize verilator variables:
QUIT_ON_VERILATOR_ERRORS -> QUIT_ON_LINTER_ERRORS
QUIT_ON_VERILATOR_WARNINGS -> QUIT_ON_LINTER_WARNINGS
VERILATOR_RELATIVE_INCLUDES -> LINTER_RELATIVE_INCLUDES
RUN_VERILATOR -> RUN_LINTER
+ add LINTER_INCLUDE_PDK_MODELS
+ add LINTER_DEFINES
+ include verilator in ci tool updater
- do not include pdk verilog models using -I
- remove workaround for verilator std error
- disallow timing constructs. Print an error to the user to remove or guard them.
~ default to lef/def in order to generate lef with pin direction (and much faster than gds)
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation
\+ Add `gui.py`. Adding the help message here:
```
Usage: gui.py [OPTIONS] RUN_DIR
View specified layout from run_dir using supported viewers
Options:
--viewer [klayout|openroad] Viewer option [default: openroad]
-f, --format [def|odb|gds] Layout format to view [default: odb]
-s, --stage [cts|floorplan|placement|routing|signoff]
Optionally specify which stage to view
--help Show this message and exit.
```
\+ Mount HOME directory when running `make mount`.
\+ Add `-congestion_report_file` to steps that call global routing
+ Add `SYNTH_MAX_TRAN` to `base.sdc` (if set)
~ Fix syntax error in `all.tcl`
- Removed attempt(s) to calculate a default value for `SYNTH_MAX_TRAN` in `all.tcl`, `openroad/cts.tcl` and `yosys/synth.tcl`
+ add `RSZ_MULTICORNER_LIB`: a flag to read multicorner libs during resizer optimizations
+ add `RSZ_LIB_FASTEST`: defaults to `LIB_FASTEST`
+ add `RSZ_LIB_SLOWEST`: defaults to `LIB_SLOWEST`
+ add `LIB_CTS_SLOWEST`
+ add `LIB_CTS_FASTEST`
+ add `CTS_MULTICONER_LIB`
~ in `read_libs`, in `scripts/openroad/common/io.tcl`, iterate over each each corner definition to allow for reading multiple files for each corner.
~ replace `-override_libs` and `-multi_corner_libs` by `-lib_fastest`, `-lib_slowest` and `-lib_typical` and modify resizer and cts tcl scripts accordingly
~ don't make copies of files in `LIB_SYNTH_COMPLETE` for `RSZ_LIB`, instead point to the original files
+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD
~ set min distance in cfg file instead of using `FP_IO_MIN_DISTANCE`
~ don't quit when min distance < legal min distance and use legal min distance. by definition if min distance is illegal it is "minimum" and we can use a higher value
~ `min_distance` is not min spacing - adjust legal tracks in `io_place.py` under that assumption
+ add wrapper.tcl to capture magic errors ported from openlane2
~ use lef/def or gds instead of mag to write a lef through MAGIC_LEF_WRITE_USE_GDS
~ print lef write log file path
Fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1701
\~ Move Yosys check quitting entirely to Python script
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
\+ Add `SYNTH_CHECKS_ALLOW_TRISTATE` that allows tristate buffers in yosys `check`
\~ Fix wrong default value of `RUN_HEURISTIC_DIODE_INSERTION` in documentation
\~ Move Yosys check quitting entirely to Python script, can ignore tristate buffer-related warnings
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
\+ Add `EXTRA_SPEFS`
\+ Use `VERILOG_FILES_BLACKBOX` in sta. Allow skipping a file by adding a comment `/// sta-blackbox`
\+ Detect blackboxed modules in typical-corner STA during sign off and warn the user about it
\+ Add `run_sta_script` used in multicorner sta
\+ Support sta in `or_issue.py`
\+ Support sta in `run_tcl_script`
\+ Check if regex defined in `FP_PDN_MACRO_HOOKS` has a match. Fixes https://github.com/The-OpenROAD-Project/OpenLane/issues/1599
\~ Wrap `set_global_connections` around a flag since it is not supported by opensta
\~ Run multicorner sta using standalone sta application for hierarchical
sta support
\~ Move `sta_multi_corner.tcl` to `scripts/openroad/sta/multi_corner.tcl`
\~ Don't delete target directory of `-save` for multicorner spef files
\~ Merge multi_corner sta and single corner into one script.
\~ Split `RUN_STANDALONE` embedded inside openroad steps, which calls sta after, to another sta step run after said openroad step
\- Remove `report_design_area` in `multi_corner.tcl` since it is not supported by standalone OpenSTA
\- Remove `scripts/openroad/sta.tcl`
~ In `yosys`, call `check -assert` at the correct stage. This requires expanding `yosys` built-in command `synth` to its original sub-commands found in https://github.com/YosysHQ/yosys/blob/master/techlibs/common/synth.cc and inject `check -assert` in the middle of the expanded command. Experimentally, this was the only way to properly capture used wires that do not have a driver.
Additional synthesis checkers guarded with `QUIT_ON_SYNTH_CHECKS`:
\+ Add `check_latches`
\+ Add `check_out_of_bound`
\+ Add `check_resizing_cell_port`
~ Fix a "resizing cell port" error in `APU` design
~ Fix a "used but has no driver" error in `tests/912`
- Deprecate DIODE_INSERTION_STRATEGY.
- Remove DIODE_INSERTION_STRATEGY 2, 1, and 5
+ Add GRT_REPAIR_ANTENNAS
+ Add HEURISTIC_ANTENNA_THRESHOLD
+ Add RUN_HEURISTIC_DIODE_INSERTION
+ Add DIODE_ON_PORTS
+ Add HEURISITIC_ANTENNA_INSERTION_MODE
~ Update benchmark results for SW_HD
~ Apply DIODE_PADDING in dpl_cell_pad which also runs after RUN_HEURISTIC_DIODE_INSERTION
run_designs.py:
~ Change default config to `config` instead of `config.json` to allow for designs with
tcl default config
~ Change logging format
+ Print SUCCESS when a design is finished
~ Use extra parameters `params.keys()` instead of `ConfigHandler.get_header()` to build
report csv header. This fixes inconsistencies between csv header and values reported
compare_regression_design.py:
~ Change metric name antenna_violations -> pin_antenna_violations
~ Handle "bad" encoding of csv report files
~ Quit when a report is perceived as invalid
~ Don't print output file name to stderr
compare_regression_reports.py:
~ Change metric name antenna_violations -> pin_antenna_violation
~ Handle "bad" encoding of csv report files
config.py:
~ Sort result from get_config_for_run and configuration_values for consistency
~ All get_config_for_run to get the full config
~ Fix antenna violations net extraction in `extract_antenna_violators.py`
~ Fix fetching antenna violation count in `generate_reports.py`
report.py:
~ Split "metric" antenna_violations to pin_antenna_violations and
net_antenna_violations as reported by openroad antenna checker
~ Add Non-phyCells
~ Add TotalCells
~ Rename cell_count to synth_cell_count to avoid confusion with TotalCells
~ Calculate cells_per_mm based on Non-phyCells instead of synth_cell_count
~ Rename
+ Add warning when attempting to run Sylvain's script without `DPL_CELL_PADDING` >= 0
+ Add warning when DPL_CELL_PADDING is set to greater than GPL_CELL_PADDING
~ Update PDK, changing the default values of GPL/DPL cell padding to `0`
~ **Use $HOME/.volare as the default PDK location**
~ `PL_TARGET_DENSITY` incorporates value of `GPL_CELL_PADDING` in calculation
~ Updated various config files to handle new default padding options
~ CI bugfixes + support for Volare 0.7.1
~ Move `QUIT_ON` variables outside of checker functions
~ Move final timing checks to a flow step: `run_timing_check_step`
~ Replace a couple of loose `file exists` with `assert_files_exist` calls
~ Replace all `flow_fail` across the flow with `throw_error`, which behaves accordingly:
* If running an interactive script, `flow_fail` is called
* Else, the errors are propagated upwards, where `flow.tcl` is to catch it
~ Rename `try_catch` to `try_exec` as it now propagates the error, with translation behavior
- Remove UMich experimental ECO flow
\+ Add `QUIT_ON_SYNTH_CHECKS` (perhaps needs a better name?)
\~ `run_tcl_script` now logs warnings to `.warnings` file
\~ `run_tcl_script` now logs errors to `.errors` file
\~ Rename `CHECK_ASSIGN_STATEMENTS` to `QUIT_ON_ASSIGN_STATEMENTS`
\~ Rename `CHECK_UNMAPPED_CELLS` to `QUIT_ON_UNMAPPED_CELLS`
\~ Fix implementation of `QUIT_ON_UNMAPPED_CELLS` by inspecting the correct yosys stat file
\~ Run `QUIT_ON_UNMAPPED_CELLS` and `QUIT_ON_ASSIGN_STATEMENTS` directly after synthesis before sta
+ Update reproducible uploading docs
+ Documented a number of missing configuration variables
~ Fix an issue where netlist STA reproducibles would attempt to use `CURRENT_ODB` and crash
- Removed a number of unused configuration variables
For `padringer.py`:
\+ Add output `ODB` and optional `DEF`
\+ Add `--odb-lef` which is the lef file to included with `ODB` output file.
\+ `--width` and `--height` are no longer required as they can be fetched from the config file
\+ `--input-lef` and `--padframe-config` click options are now multiple
others:
\+ Add `FP_PADFRAME_CFG` which points to configuration file passed to `padringer.py`
\+ Add `GPIO_PADS_PREFIX` to parameterize prefix passed to `padringer.py`
\+ Add `padframe_gen_batch` to capture all of the above in a simple wrapper
\+ Add klayoutrc to OL images
\+ Made klayout scripts launchable as commands
\+ Add new quit_on_xor_error checker
\+ Add `KLAYOUT_XOR_THREADS`
\~ Rewrite XOR script to be more readable
\~ klayout -> 8bed8bcc3ca19f7e1a810815541977fd16bc1db5
\- Remove KLAYOUT_XOR_GDS, KLAYOUT_XOR_XML: XML only now
\- Remove mv_shapes: unused
Co-authored-by: Kareem Farid <karimmhany@gmail.com>
+ Add JSON support to "matrix" mode
~ Rename "regression mode" to "matrix", as it more accurately reflects a combination of variables
~ Replace bizzare "regression script" with a JSON file achieving basically the same thing
~ `run_designs` now clears run paths before it starts
~ `run_designs` no longer attempts to generated reports for runs that fail at startup
~ `verify_versions` no longer attempts to check the PDK if the environment variable PDK is not set
~ `scripts/config/config.py:get_config` -> `get_config_for_run` (more accurate)
~ `scripts/config/tcl.py:read_tcl_env` no longer exits unilaterally, raises an exception normally
- Remove Test #892
- Remove `Tcl` support from matrix mode: not tenable
- Remove Tcl extraction shell script
---
Resolves#1458
\~ document the right report file for `run_or_antenna_check`
\~ fetch the correct report/log file for openroad antenna reports
\~ capture pin violations and net violations
\~ fetch the correct report file for magic antenna report
~ fix cell name in `user_proj_example2.gds` in `caravel_upw` testcase. the cell name was incorrectly set to `user_proj_example`
~ update magic version.
+ add configuration variable `MAGIC_GDS_ALLOW_ABSTRACT` to allow abstract view of macros during magic gds generation which was previously allowed in magic. The new default is set to disallowed as usually having abstract view is caused by an error in configuration.
~ check the right flags while setting pin thickness and multiplier
~ change default values of FP_IO_*EXTEND to 0
Co-authored-by: Donn <me@donn.website>
+ Add test for JSON config files
~ Updated various `rm` execs to `file delete -force`
~ Test script now outputs to stdout as well as a log file
~ Moved post-run hook runner to `all.tcl`
~ Moved installation docs to their own subcategory
~ Fix security bug
+ Add yosys to `run_tcl_script`, enabling the automatic production of reproducibles
~ yosys -> f109fa3d4c56fe33bc626c298e04d45ae510dd0e
~ Cleaned up LEC script a bit (thanks @emjunaid for initial work)
~ Fix bug where cell_count was not extracted properly
- Removed `get_yosys_bin`: It's been deprecated forever
\+ Add PDK variable `WIRE_LENGTH_THRESHOLD` which wires with lengths >= said value are flagged
\+ Add `QUIT_ON_LONG_WIRE` which fails the flow if any wires are flagged for length
~ Update all `$::env(OPENROAD_BIN) -exit -python` invocations to include `-no_init` to suppress message about rc file
~ Replace ill-fitting `$::env(OPENROAD_BIN) -exit -python` invocations with just `python3`
~ Replace local install check with a simple git directory check
+ Formalized concept of "exposed variables", environment variables that are exposed to `config.json` during processing
+ `dir::` is no longer a special case: all `ref::` prefices referencing a path now have the ability to glob inside said path
+ Made `dir::`, `pdk_dir::` and `scl_dir::` short-hands for various `ref::`s
+ Add `proc erase_box` to OpenLane
+ Add two new config variables for magic def reads: `MAGIC_DEF_NO_BLOCKAGES` and `MAGIC_DEF_LABELS`
~ Magic scripts hierachically organized by input format
~ `erase_box.sh` deprecated
~ More decisively separate LVS logs from reports
+ Add flag to enable/disable timing model generation after STA
+ Add both powered and unpowered netlists to `save_views`
+ Add multi-corner SDF and SPEF files to `save_views`
~ Fix#1413 and add regression test
~ Move `./run_issue_regressions.py` inside `tests` as a modular main function
+ Create `RCX_SDC_FILE` as an optional SDC file to be used only for parasitics extraction (and consequent STA)
+ Document `SYNTH_ELABORATE_ONLY`, which only elaborates structured netlists without an attempt at logic mapping ~ Add translation behavior from previous, ambiguously named `SYNTH_TOP_LEVEL` to `SYNTH_ELABORATE_ONLY`
~ `scripts/yosys/synth_top.tcl` -> `elaborate.tcl`
~ Documentation consistency fixes
~ Fix wildcard in `docker/Makefile`
+ Add calls to `set_dont_touch` and then `unset_dont_touch` at the beginning and end of every resizer script respectively ~ Reorganize config variables
+ Added undocumented variable `RSZ_USE_OLD_REMOVER` to continue to use the old `remove_buffers.py` script instead
~ `LIB_RESIZER_OPT` -> `RSZ_LIB` (with translation behavior)
~ `UNBUFFER_NETS` -> `RSZ_DONT_TOUCH_RX` (with translation behavior)
~ Made timing models only get written after CTS by checking for `STA_PRE_CTS` as well
