mirror of
https://github.com/The-OpenROAD-Project/TritonRoute.git
synced 2026-05-30 00:06:29 +08:00
create golden file for unit test and actually check it
This commit is contained in:
Matt Liberty
1
.gitignore
vendored
1
.gitignore
vendored
@@ -4,5 +4,6 @@ build
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build/*.*
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Makefile
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*.log
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!**/golden/*.log
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module/def/5.8-p029/def.output
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@@ -11,19 +11,36 @@ set test_drc [format "%12d" 0]
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set golden_drc [format "%12d" 0]
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if {[file exists $golden_log]} {
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catch {set golden_wirelength [format "%12d" [exec grep -e {total wire length = } $golden_log | tail -1 awk {{print $5}}]]}
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catch {set golden_via [format "%12d" [exec grep -e {total number of vias = } $golden_log | tail -1 awk {{print $6}}]]}
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catch {set golden_drc [format "%12d" [exec grep -e {number of violations = } $golden_log | tail -1 awk {{print $5}}]]}
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set golden_wirelength [format "%12d" [exec grep -e {total wire length = } $golden_log | tail -1 | awk {{print $5}}]]
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set golden_via [format "%12d" [exec grep -e {total number of vias = } $golden_log | tail -1 | awk {{print $6}}]]
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set golden_drc [format "%12d" [exec grep -e {number of violations = } $golden_log | tail -1 | awk {{print $5}}]]
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} else {
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puts "golden file $golden_log not found"
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exit 1
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}
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if {[file exists $test_log]} {
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catch {set test_wirelength [format "%12d" [exec grep -e {total wire length = } $test_log | tail -1 awk {{print $5}}]]}
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catch {set test_via [format "%12d" [exec grep -e {total number of vias = } $test_log | tail -1 awk {{print $6}}]]}
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catch {set test_drc [format "%12d" [exec grep -e {number of violations = } $test_log | tail -1 awk {{print $5}}]]}
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set test_wirelength [format "%12d" [exec grep -e {total wire length = } $test_log | tail -1 | awk {{print $5}}]]
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set test_via [format "%12d" [exec grep -e {total number of vias = } $test_log | tail -1 | awk {{print $6}}]]
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set test_drc [format "%12d" [exec grep -e {number of violations = } $test_log | tail -1 | awk {{print $5}}]]
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} else {
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puts "test file $test_log not found"
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exit 1
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}
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if { $golden_wirelength >= $test_wirelength && $golden_via >= $test_via && $golden_drc >= $test_drc } {
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exit 0
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} else {
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if { $golden_wirelength < $test_wirelength } {
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puts "Wire Length: golden=$golden_wirelength test=$test_wirelength"
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exit 1
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}
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}
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if { $golden_via < $test_via } {
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puts "Vias: golden=$golden_via test=$test_via"
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exit 1
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}
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if { $golden_drc < $test_drc } {
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puts "DRC: golden=$golden_drc test=$test_drc"
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exit 1
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}
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exit 0
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614
test/testcase/ispd18_sample/golden/ispd18_sample.log
Normal file
614
test/testcase/ispd18_sample/golden/ispd18_sample.log
Normal file
@@ -0,0 +1,614 @@
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reading lef ...
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USEMINSPACING OBS ON
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule
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Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH
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units: 2000
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#layers: 19
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#macros: 16
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#vias: 22
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#viarulegen: 0
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reading def ...
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design: ispd18_sample
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die area: ( 83600 71820 ) ( 104400 91200 )
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trackPts: 18
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defvias: 0
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#components: 22
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#terminals: 0
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#snets: 0
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#nets: 11
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reading guide ...
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#guides: 52
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Warning: Metal5 does not have viaDef align with layer direction, generating new viaDef Via5_FR...
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Warning: Metal6 does not have viaDef align with layer direction, generating new viaDef Via6_FR...
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Warning: Metal7 does not have viaDef align with layer direction, generating new viaDef Via7_FR...
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done initConstraintLayerIdx
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List of default vias:
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Layer Via1
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default via: VIA12_1C
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Layer Via2
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default via: VIA23_1C
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Layer Via3
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default via: VIA34_1C
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Layer Via4
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default via: VIA45_1C
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Layer Via5
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default via: Via5_FR
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Layer Via6
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default via: Via6_FR
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Layer Via7
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default via: Via7_FR
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Layer Via8
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default via: VIA8_0_VH
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Writing reference output def...
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libcell analysis ...
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instance analysis ...
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#unique instances = 17
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init region query ...
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complete FR_MASTERSLICE
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complete FR_VIA
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complete Metal1
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complete Via1
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complete Metal2
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complete Via2
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complete Metal3
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complete Via3
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complete Metal4
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complete Via4
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complete Metal5
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complete Via5
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complete Metal6
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complete Via6
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complete Metal7
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complete Via7
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complete Metal8
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complete Via8
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complete Metal9
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FR_MASTERSLICE shape region query size = 0
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FR_VIA shape region query size = 0
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Metal1 shape region query size = 344
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Via1 shape region query size = 0
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Metal2 shape region query size = 0
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Via2 shape region query size = 0
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Metal3 shape region query size = 0
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Via3 shape region query size = 0
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Metal4 shape region query size = 0
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Via4 shape region query size = 0
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Metal5 shape region query size = 0
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Via5 shape region query size = 0
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Metal6 shape region query size = 0
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Via6 shape region query size = 0
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Metal7 shape region query size = 0
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Via7 shape region query size = 0
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Metal8 shape region query size = 0
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Via8 shape region query size = 0
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Metal9 shape region query size = 0
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start pin access
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complete 79 pins
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complete 17 unique inst patterns
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complete 19 groups
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Expt1 runtime (pin-level access point gen): 0.183736
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Expt2 runtime (design-level access pattern gen): 0.127199
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#scanned instances = 22
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#unique instances = 17
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#stdCellGenAp = 396
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#stdCellValidPlanarAp = 0
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#stdCellValidViaAp = 352
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#stdCellPinNoAp = 0
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#stdCellPinCnt = 22
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#instTermValidViaApCnt = 0
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#macroGenAp = 0
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#macroValidPlanarAp = 0
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#macroValidViaAp = 0
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#macroNoAp = 0
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complete pin access
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cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.34 (MB), peak = 4.42 (MB)
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post process guides ...
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GCELLGRID X 71820 DO 3 STEP 5700 ;
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GCELLGRID Y 83600 DO 3 STEP 6000 ;
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complete FR_MASTERSLICE
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complete FR_VIA
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complete Metal1
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complete Via1
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complete Metal2
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complete Via2
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complete Metal3
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complete Via3
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complete Metal4
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complete Via4
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complete Metal5
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complete Via5
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complete Metal6
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complete Via6
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complete Metal7
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complete Via7
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complete Metal8
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complete Via8
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complete Metal9
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building cmap ...
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init guide query ...
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complete FR_MASTERSLICE (guide)
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complete FR_VIA (guide)
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complete Metal1 (guide)
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complete Via1 (guide)
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complete Metal2 (guide)
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complete Via2 (guide)
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complete Metal3 (guide)
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complete Via3 (guide)
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complete Metal4 (guide)
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complete Via4 (guide)
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complete Metal5 (guide)
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complete Via5 (guide)
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complete Metal6 (guide)
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complete Via6 (guide)
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complete Metal7 (guide)
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complete Via7 (guide)
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complete Metal8 (guide)
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complete Via8 (guide)
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complete Metal9 (guide)
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FR_MASTERSLICE guide region query size = 0
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FR_VIA guide region query size = 0
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Metal1 guide region query size = 22
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Via1 guide region query size = 0
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Metal2 guide region query size = 22
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Via2 guide region query size = 0
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Metal3 guide region query size = 10
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Via3 guide region query size = 0
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Metal4 guide region query size = 0
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Via4 guide region query size = 0
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Metal5 guide region query size = 0
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Via5 guide region query size = 0
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Metal6 guide region query size = 0
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Via6 guide region query size = 0
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Metal7 guide region query size = 0
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Via7 guide region query size = 0
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Metal8 guide region query size = 0
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Via8 guide region query size = 0
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Metal9 guide region query size = 0
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init gr pin query ...
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Waring: no output guide specified, skipped writing guide
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start track assignment
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Done with 22 vertical wires in 1 frboxes and 32 horizontal wires in 1 frboxes.
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Done with 2 vertical wires in 1 frboxes and 1 horizontal wires in 1 frboxes.
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complete track assignment
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cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.42 (MB), peak = 4.67 (MB)
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Waring: no output def specified, skipped writing track assignment def
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start routing data preparation
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initVia2ViaMinLen_minSpc Metal1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 380)
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initVia2ViaMinLen_minSpc Metal2 (d2d, d2u, u2d, u2u) = (260, 0, 0, 280)
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initVia2ViaMinLen_minSpc Metal3 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minSpc Metal4 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minSpc Metal5 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minSpc Metal6 (d2d, d2u, u2d, u2u) = (280, 0, 0, 1340)
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initVia2ViaMinLen_minSpc Metal7 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340)
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initVia2ViaMinLen_minSpc Metal8 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340)
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initVia2ViaMinLen_minSpc Metal9 (d2d, d2u, u2d, u2u) = (1340, 0, 0, 0)
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initVia2ViaMinLen_minimumcut Metal1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 380)
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initVia2ViaMinLen_minimumcut Metal1 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal2 (d2d, d2u, u2d, u2u) = (260, 0, 0, 280)
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initVia2ViaMinLen_minimumcut Metal2 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal3 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minimumcut Metal3 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal4 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minimumcut Metal4 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal5 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280)
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initVia2ViaMinLen_minimumcut Metal5 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal6 (d2d, d2u, u2d, u2u) = (280, 0, 0, 1340)
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initVia2ViaMinLen_minimumcut Metal6 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal7 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340)
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initVia2ViaMinLen_minimumcut Metal7 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal8 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340)
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initVia2ViaMinLen_minimumcut Metal8 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLen_minimumcut Metal9 (d2d, d2u, u2d, u2u) = (1340, 0, 0, 0)
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initVia2ViaMinLen_minimumcut Metal9 zerolen (b, b, b, b) = (1, 1, 1, 1)
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initVia2ViaMinLenNew_minSpc Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400)
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initVia2ViaMinLenNew_minSpc Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 260, 280, 0, 280, 0, 400, 280)
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initVia2ViaMinLenNew_minSpc Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
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initVia2ViaMinLenNew_minSpc Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280)
|
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initVia2ViaMinLenNew_minSpc Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
|
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initVia2ViaMinLenNew_minSpc Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minSpc Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minSpc Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minSpc Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0)
|
||||
initVia2ViaMinLenNew_minimumcut Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400)
|
||||
initVia2ViaMinLenNew_minimumcut Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 260, 280, 0, 280, 0, 400, 280)
|
||||
initVia2ViaMinLenNew_minimumcut Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
|
||||
initVia2ViaMinLenNew_minimumcut Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280)
|
||||
initVia2ViaMinLenNew_minimumcut Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
|
||||
initVia2ViaMinLenNew_minimumcut Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minimumcut Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minimumcut Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340)
|
||||
initVia2ViaMinLenNew_minimumcut Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0)
|
||||
initVia2ViaMinLenNew_cutSpc Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400)
|
||||
initVia2ViaMinLenNew_cutSpc Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 280, 280, 0, 280, 0, 400, 280)
|
||||
initVia2ViaMinLenNew_cutSpc Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
|
||||
initVia2ViaMinLenNew_cutSpc Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280)
|
||||
initVia2ViaMinLenNew_cutSpc Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400)
|
||||
initVia2ViaMinLenNew_cutSpc Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340)
|
||||
initVia2ViaMinLenNew_cutSpc Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340)
|
||||
initVia2ViaMinLenNew_cutSpc Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340)
|
||||
initVia2ViaMinLenNew_cutSpc Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0)
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.67 (MB), peak = 4.71 (MB)
|
||||
|
||||
start detail routing ...
|
||||
start 0th optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 5.73 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 5.88 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 1st optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 6.39 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 2nd optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 20% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 30% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 40% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 17th optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 25th optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 33rd optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 20% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 30% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 40% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 41st optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 20% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 30% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 40% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 49th optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
start 57th optimization iteration ...
|
||||
completing 10% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 20% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 30% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
completing 40% with 0 violations
|
||||
elapsed time = 00:00:00, memory = 12.34 (MB)
|
||||
number of violations = 0
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
|
||||
complete detail routing
|
||||
total wire length = 77 um
|
||||
total wire length on LAYER Metal1 = 2 um
|
||||
total wire length on LAYER Metal2 = 31 um
|
||||
total wire length on LAYER Metal3 = 43 um
|
||||
total wire length on LAYER Metal4 = 0 um
|
||||
total wire length on LAYER Metal5 = 0 um
|
||||
total wire length on LAYER Metal6 = 0 um
|
||||
total wire length on LAYER Metal7 = 0 um
|
||||
total wire length on LAYER Metal8 = 0 um
|
||||
total wire length on LAYER Metal9 = 0 um
|
||||
total number of vias = 44
|
||||
up-via summary (total 44):
|
||||
|
||||
---------------------
|
||||
FR_MASTERSLICE 0
|
||||
Metal1 24
|
||||
Metal2 20
|
||||
Metal3 0
|
||||
Metal4 0
|
||||
Metal5 0
|
||||
Metal6 0
|
||||
Metal7 0
|
||||
Metal8 0
|
||||
---------------------
|
||||
44
|
||||
|
||||
cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB)
|
||||
|
||||
post processing ...
|
||||
|
||||
Runtime taken (hrt): 1.23143
|
||||
Reference in New Issue
Block a user