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The-OpenROAD-Project/ OpenLane

Python 0 0

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Updated 2025-09-16 02:32:50 +08:00