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verilator/ verilator

Verilator open-source SystemVerilog simulator and lint system

compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator

Updated 2026-05-29 18:26:07 +08:00

The-OpenROAD-Project/ OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog

Updated 2026-05-28 02:24:39 +08:00

chipsalliance/ chisel

Scala 0 0

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Updated 2026-05-12 11:13:14 +08:00

freechipsproject/ rocket-chip

Scala 0 0

Rocket Chip Generator

chip-generator chisel riscv rocket-chip rtl scala

Updated 2026-04-22 06:24:29 +08:00

The-OpenROAD-Project/ OpenLane

Python 0 0

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Updated 2025-09-16 02:32:50 +08:00

syntacore/ scr1

SystemVerilog 0 0

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog

Updated 2024-11-15 22:22:48 +08:00