~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)
+ Add tt05-i2c-bert (https://github.com/dlmiles/tt05-i2c-bert) to CI
~ Replace instances of ABC command `rewrite` with `drw -l` with `SYNTH_ABC_LEGACY_REWRITE` being set to `1` restoring the older functionality (`0` by default)
~ Replace instances of ABC command `refactor` with `drf -l` with `SYNTH_ABC_LEGACY_REFACTOR` being set to `1` restoring the older functionality (`0` by default)
~ Added `delete t:\$print` to `synth.tcl` to fix designs such as PPU with synthesized prints (as in https://github.com/efabless/openlane2/pull/189)
---------
Co-authored-by: Mohamed Gaber <donn@efabless.com>
~ Set default `FP_IO_MODE` to 0.
~ Better `FP_IO_MODE` documentation.
~ Change the behavior of `FP_IO_MODE` 0:
1. Run global placement with `-skip_io` flag.
2. Run io placement (again).
3. Run global placement.
If `FP_IO_MODE` is 1, steps 1 and 2 are skipped.
~ Change tcl functions `global_placement_or` and `place_io` to allow for the changes mentioned above.
~ Fix issue where `PNR_SDC_FILE` and `SIGNOFF_SDC_FILE` were set too early and were not affected by changes to values of `BASE_SDC_FILE` in user config
+ Add PNR_SDC_FILE
+ Warn when (PNR|SIGNOFF)_SDC_FILE are not overwritten by the user.
+ Add SDC_IN and DEFAULT_SDC_FILE to ignore list in CI
+ Add per corner max slew/fanout/cap count to sta report
+ Add per corner worst hold and setup value to sta report
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Always use PNR_SDC_FILE instead of CURRENT_SDC except during signoff stage, where SIGNOFF_SDC_FILE is used instead
~ Enable DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION for APU which fails after SDC updates.
~ Adjust timing checkers according to the new reported values
+ add `generate_blackbox_verilog` that generates a black-boxed header file from a list of Verilog models
+ add `scripts/synth/blackbox.tcl` for `generate_blackbox_verilog`
+ use `generate_blackbox_verilog` with `VERILOG_FILES_BLACKBOX` and PDK verilog models
+ disable `UNDRIVEN` and `UNUSEDSIGNAL` for PDK verilog files
+ add `YOSYS_IN`, `YOSYS_OUT`, `YOSYS_DEFINES` which are used in blackbox.tcl
to internal variables in ci variables documentation workflow
~ enable `LINTER_INCLUDE_PDK_MODELS`
Co-authored-by: Donn <me@donn.website>
+ Warn when IMPLEMENTATION_SDC_FILE is not overwritten by the user.
+ Add SDC_IN and IMPLEMENTATION_SDC_FILE_DEFAULT to ignore list in ci Check Variables flow
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Rename BASE_SDC_FILE to IMPLEMENTATION_SDC_FILE.
~ Always use IMPLMEMENTATION_SDC_FILE instead of CURRENT_SDC except during signoff stage
+ Added `make docs` target to primary Makefile to generate documentation
~ Update documentation dependencies
~ Updated `tcl.py` to handle JSON lists of elements including whitespace by joining them with a comma (unless one of the elements already contains a comma), resolving odd JSON syntax
~ Re-organized and re-order configuration variables and edited descriptions for general consistency as well as adding anchors
~ Update all documentation dependencies
~ Fixed a number of broken links
- Remove dependency on `docutils` and `sphinx-autobuild` (both unused)
- Remove two of the custom documentation extensions
~ Classified PDK variables by user modifiability
~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT`
~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT`
~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD`
- Removed `DEFAULT_MAX_TRAN` from PDK (unused)
Script uses regular expressions to create a set of documents variables and a set of used variables and compare them against each other. Some variables are internal, unexposed and others. These variables are whitelisted. See https://github.com/The-OpenROAD-Project/OpenLane/issues/1889
\+ Add documentation for `QUIT_ON_XOR_ERROR`
~ generalize verilator variables:
QUIT_ON_VERILATOR_ERRORS -> QUIT_ON_LINTER_ERRORS
QUIT_ON_VERILATOR_WARNINGS -> QUIT_ON_LINTER_WARNINGS
VERILATOR_RELATIVE_INCLUDES -> LINTER_RELATIVE_INCLUDES
RUN_VERILATOR -> RUN_LINTER
+ add LINTER_INCLUDE_PDK_MODELS
+ add LINTER_DEFINES
+ include verilator in ci tool updater
- do not include pdk verilog models using -I
- remove workaround for verilator std error
- disallow timing constructs. Print an error to the user to remove or guard them.
~ default to lef/def in order to generate lef with pin direction (and much faster than gds)
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation
the whole point of the powered def is to compare the power connections
of the rtl with the power connections defined in macro hooks. the
current implementation writes a def file generated from a netlist
created from the rtl and the final def generated after routing. this is
done in a python script followed by a tcl call to `write_verilog`
because there isn't a python api for writing verilog. this introduced a
problem where during `write_verilog` global connections defined in macro
hooks are set overwriting whatever changes to the power connections made in
the powered def. this pr add -no_global_connect during the
`write_verilog` step to avoid the override mentioned earlier.
+ add `RSZ_MULTICORNER_LIB`: a flag to read multicorner libs during resizer optimizations
+ add `RSZ_LIB_FASTEST`: defaults to `LIB_FASTEST`
+ add `RSZ_LIB_SLOWEST`: defaults to `LIB_SLOWEST`
+ add `LIB_CTS_SLOWEST`
+ add `LIB_CTS_FASTEST`
+ add `CTS_MULTICONER_LIB`
~ in `read_libs`, in `scripts/openroad/common/io.tcl`, iterate over each each corner definition to allow for reading multiple files for each corner.
~ replace `-override_libs` and `-multi_corner_libs` by `-lib_fastest`, `-lib_slowest` and `-lib_typical` and modify resizer and cts tcl scripts accordingly
~ don't make copies of files in `LIB_SYNTH_COMPLETE` for `RSZ_LIB`, instead point to the original files
+ add STA_MULTICORNER_READ_LIBS to pick between reading liberties vs reading verilog + spefs - undocumented
+ add reading CURRENT_SPEF in function `read`
+ add ability to not read EXTRA_LIBS in function `read_libs`
+ sta/multi_corner.tcl should now work with openroad
+ add -estimate_global and -estimate_placement to `run_sta` and used it whenever applicable: See https://github.com/The-OpenROAD-Project/OpenROAD/discussions/3287
+ add -tool to run_sta to switch between openroad and opensta
+ use -pre_cts whenever applicable
~ fix a bug where EXTRA_SPEFS aren't properly loading. Fix is accomplished by passing PROCESS_CORNER to multi_corner.tcl script.
+ add verfied scl to verilator verified list. sky130_fd_sc_hs had verilator errors in its verilog models
~ fix wrong usage of FP_IO_HLENGTH. should be FP_IO_VLENGTH
~ restore `report_design_area` in STA.
+ add `report_design_area` in resizer scripts to see the impact of resizer, in terms of utilization
+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD
+ add wrapper.tcl to capture magic errors ported from openlane2
~ use lef/def or gds instead of mag to write a lef through MAGIC_LEF_WRITE_USE_GDS
~ print lef write log file path
Fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1701
\~ Move Yosys check quitting entirely to Python script
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
\+ Add `SYNTH_CHECKS_ALLOW_TRISTATE` that allows tristate buffers in yosys `check`
\~ Fix wrong default value of `RUN_HEURISTIC_DIODE_INSERTION` in documentation
\~ Move Yosys check quitting entirely to Python script, can ignore tristate buffer-related warnings
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
- Deprecate DIODE_INSERTION_STRATEGY.
- Remove DIODE_INSERTION_STRATEGY 2, 1, and 5
+ Add GRT_REPAIR_ANTENNAS
+ Add HEURISTIC_ANTENNA_THRESHOLD
+ Add RUN_HEURISTIC_DIODE_INSERTION
+ Add DIODE_ON_PORTS
+ Add HEURISITIC_ANTENNA_INSERTION_MODE
~ Update benchmark results for SW_HD
~ Apply DIODE_PADDING in dpl_cell_pad which also runs after RUN_HEURISTIC_DIODE_INSERTION
run_designs.py:
~ Change default config to `config` instead of `config.json` to allow for designs with
tcl default config
~ Change logging format
+ Print SUCCESS when a design is finished
~ Use extra parameters `params.keys()` instead of `ConfigHandler.get_header()` to build
report csv header. This fixes inconsistencies between csv header and values reported
compare_regression_design.py:
~ Change metric name antenna_violations -> pin_antenna_violations
~ Handle "bad" encoding of csv report files
~ Quit when a report is perceived as invalid
~ Don't print output file name to stderr
compare_regression_reports.py:
~ Change metric name antenna_violations -> pin_antenna_violation
~ Handle "bad" encoding of csv report files
config.py:
~ Sort result from get_config_for_run and configuration_values for consistency
~ All get_config_for_run to get the full config
~ Fix antenna violations net extraction in `extract_antenna_violators.py`
~ Fix fetching antenna violation count in `generate_reports.py`
report.py:
~ Split "metric" antenna_violations to pin_antenna_violations and
net_antenna_violations as reported by openroad antenna checker
~ Add Non-phyCells
~ Add TotalCells
~ Rename cell_count to synth_cell_count to avoid confusion with TotalCells
~ Calculate cells_per_mm based on Non-phyCells instead of synth_cell_count
~ Rename
~ Move `QUIT_ON` variables outside of checker functions
~ Move final timing checks to a flow step: `run_timing_check_step`
~ Replace a couple of loose `file exists` with `assert_files_exist` calls
~ Replace all `flow_fail` across the flow with `throw_error`, which behaves accordingly:
* If running an interactive script, `flow_fail` is called
* Else, the errors are propagated upwards, where `flow.tcl` is to catch it
~ Rename `try_catch` to `try_exec` as it now propagates the error, with translation behavior
- Remove UMich experimental ECO flow
\+ Add `QUIT_ON_SYNTH_CHECKS` (perhaps needs a better name?)
\~ `run_tcl_script` now logs warnings to `.warnings` file
\~ `run_tcl_script` now logs errors to `.errors` file
\~ Rename `CHECK_ASSIGN_STATEMENTS` to `QUIT_ON_ASSIGN_STATEMENTS`
\~ Rename `CHECK_UNMAPPED_CELLS` to `QUIT_ON_UNMAPPED_CELLS`
\~ Fix implementation of `QUIT_ON_UNMAPPED_CELLS` by inspecting the correct yosys stat file
\~ Run `QUIT_ON_UNMAPPED_CELLS` and `QUIT_ON_ASSIGN_STATEMENTS` directly after synthesis before sta
\+ Add `KLAYOUT_DEF_LAYER_MAP` for DEF/LEF mapping in klayout. `.lyt` is not sufficient to map a pin shape to pin and metal for example.
\+ Add `KLAYOUT_XOR_IGNORE_LAYERS` see https://github.com/RTimothyEdwards/open_pdks/pull/347 (default: empty)
\~ Enable `QUIT_ON_XOR_ERROR` by default
\+ Add klayoutrc to OL images
\+ Made klayout scripts launchable as commands
\+ Add new quit_on_xor_error checker
\+ Add `KLAYOUT_XOR_THREADS`
\~ Rewrite XOR script to be more readable
\~ klayout -> 8bed8bcc3ca19f7e1a810815541977fd16bc1db5
\- Remove KLAYOUT_XOR_GDS, KLAYOUT_XOR_XML: XML only now
\- Remove mv_shapes: unused
Co-authored-by: Kareem Farid <karimmhany@gmail.com>
~ fix cell name in `user_proj_example2.gds` in `caravel_upw` testcase. the cell name was incorrectly set to `user_proj_example`
~ update magic version.
+ add configuration variable `MAGIC_GDS_ALLOW_ABSTRACT` to allow abstract view of macros during magic gds generation which was previously allowed in magic. The new default is set to disallowed as usually having abstract view is caused by an error in configuration.
~ check the right flags while setting pin thickness and multiplier
~ change default values of FP_IO_*EXTEND to 0
Co-authored-by: Donn <me@donn.website>
\+ Add PDK variable `WIRE_LENGTH_THRESHOLD` which wires with lengths >= said value are flagged
\+ Add `QUIT_ON_LONG_WIRE` which fails the flow if any wires are flagged for length
~ Update all `$::env(OPENROAD_BIN) -exit -python` invocations to include `-no_init` to suppress message about rc file
~ Replace ill-fitting `$::env(OPENROAD_BIN) -exit -python` invocations with just `python3`
~ Replace local install check with a simple git directory check
+ Add `proc erase_box` to OpenLane
+ Add two new config variables for magic def reads: `MAGIC_DEF_NO_BLOCKAGES` and `MAGIC_DEF_LABELS`
~ Magic scripts hierachically organized by input format
~ `erase_box.sh` deprecated
~ More decisively separate LVS logs from reports
+ Add flag to enable/disable timing model generation after STA
+ Add both powered and unpowered netlists to `save_views`
+ Add multi-corner SDF and SPEF files to `save_views`
~ Fix#1413 and add regression test
~ Move `./run_issue_regressions.py` inside `tests` as a modular main function
+ Create `RCX_SDC_FILE` as an optional SDC file to be used only for parasitics extraction (and consequent STA)
+ Document `SYNTH_ELABORATE_ONLY`, which only elaborates structured netlists without an attempt at logic mapping ~ Add translation behavior from previous, ambiguously named `SYNTH_TOP_LEVEL` to `SYNTH_ELABORATE_ONLY`
~ `scripts/yosys/synth_top.tcl` -> `elaborate.tcl`
~ Documentation consistency fixes
~ Fix wildcard in `docker/Makefile`
+ Add calls to `set_dont_touch` and then `unset_dont_touch` at the beginning and end of every resizer script respectively ~ Reorganize config variables
+ Added undocumented variable `RSZ_USE_OLD_REMOVER` to continue to use the old `remove_buffers.py` script instead
~ `LIB_RESIZER_OPT` -> `RSZ_LIB` (with translation behavior)
~ `UNBUFFER_NETS` -> `RSZ_DONT_TOUCH_RX` (with translation behavior)
~ Made timing models only get written after CTS by checking for `STA_PRE_CTS` as well
+ Add gf180mcuC configs for {APU, PPU, SPM}
~ Clean up some leftover variables
~ STD_CELL_LIBRARY now an optional environment variable- open_pdks config files are now responsible for setting the default
~ `to_tcl.py` updated to reflect that ^
~ Add ability to just set `METAL_LAYER_NAMES` in open_pdks
~ `open_pdks` -> 44a43c23c81b45b8e774ae7a84899a5a778b6b0b
+ `UNBUFFER_NETS` created, which takes a regular expression, which if matched, remove buffers from said net
~ `scripts/odbpy/remove_buffers.py` rewritten to be comprehensible
~ `remove_buffers_from_ports` -> `remove_buffers_from_nets`, now runs after every resizer step
~ `remove_*` python commands now only use regular expressions
- Remove `DONT_BUFFER_PORTS` as the name does not reflect the proactive nature of buffer removal
- Remove `remove_component` (singular)- unused
This is a temporary workaround until a proper "don't touch net" feature is available in OpenROAD.
