Commit Graph

192 Commits

Author SHA1 Message Date
Kareem Farid
571581d5b7 Integrate KLayout DRC for sky130 (#2059)
~ Bump open_pdks version to `cd1748bb197f9b7af62a54507de6624e30363943`
~ Rename `PRIMARY_SIGNOFF_TOOL` to `PRIMARY_GDSII_STREAMOUT_TOOL`
~ Update documentation of `RUN_MAGIC_DRC` and `RUN_KLAYOUT_DRC`
+ Integrate KLayout DRC for sky130
+ Add the following variables:
```
KLAYOUT_DRC_THREADS
QUIT_ON_KLAYOUT_DRC
RUN_KLAYOUT_DRC
KLAYOUT_DRC_RUNSET - PDK variable
KLAYOUT_DRC_OPTIONS - PDK variable
```
- Remove `KLAYOUT_DRC_KLAYOUT_GDS`
2023-12-11 17:31:54 +02:00
Darryl Miles
f691c8c071 yosys/synth.tcl: migrate to newer supported drw & drf commands (#2051)
+ Add tt05-i2c-bert (https://github.com/dlmiles/tt05-i2c-bert) to CI
~ Replace instances of ABC command `rewrite` with `drw -l` with `SYNTH_ABC_LEGACY_REWRITE` being set to `1` restoring the older functionality (`0` by default)
~ Replace instances of ABC command `refactor` with `drf -l` with `SYNTH_ABC_LEGACY_REFACTOR` being set to `1` restoring the older functionality (`0` by default)
~ Added `delete t:\$print` to `synth.tcl` to fix designs such as PPU with synthesized prints (as in https://github.com/efabless/openlane2/pull/189)

---------

Co-authored-by: Mohamed Gaber <donn@efabless.com>
2023-11-22 15:45:53 +02:00
Mohamed Gaber
ee452da40d Issue Survey Fixes (#2056)
~ Updated install documentation
~ Fixed issue where the issue survey's PDK checker uses `./pdks` instead of `~/.volare`
- Dropped `pip` requirement/check: `venv`s include `pip` regardless
2023-11-22 10:46:09 +02:00
Mohamed Gaber
747bdbbd2d Makefile Improvements + Banner Update (#2018)
+ Added a new target to the Makefile, `make m`, which mounts the directory at the same path in the container as it is in the host
~ Changed Makefile to mount an empty folder where `install` is so there's less confusion
~ Updated banner per @shalan's recommendation
- Remove `make veryclean` which users may not use consciously and end up nuking their designs
2023-10-19 17:34:52 +03:00
Kareem Farid
57f8254c4f Fix reference to example matrix.json file in documentation (#2011) 2023-10-04 11:29:17 +03:00
Kareem Farid
5771836bf4 Add -skip_io and iterate io and global placement (#1984)
~ Set default `FP_IO_MODE` to 0.
~ Better `FP_IO_MODE` documentation.
~ Change the behavior of `FP_IO_MODE` 0:
1. Run global placement with `-skip_io` flag. 
2. Run io placement (again).
3. Run global placement.

If `FP_IO_MODE` is 1, steps 1 and 2 are skipped. 

~ Change tcl functions `global_placement_or` and `place_io` to allow for the changes mentioned above.
2023-10-01 15:19:35 +00:00
Mohamed Gaber
456838bffc Remove CVC (#1976)
- Remove `cvc_rv` utility (upstream no longer willing to support it as part of the flow)
~ Fix bug with OpenLane docker image builder copying run folders
2023-09-06 14:48:32 +03:00
Kareem Farid
5fb033caa0 SDC Behavior Overhaul (#1944)
+ Add PNR_SDC_FILE
+ Warn when (PNR|SIGNOFF)_SDC_FILE are not overwritten by the user.
+ Add SDC_IN and DEFAULT_SDC_FILE to ignore list in CI
+ Add per corner max slew/fanout/cap count to sta report
+ Add per corner worst hold and setup value to sta report 
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Always use PNR_SDC_FILE instead of CURRENT_SDC except during signoff stage, where SIGNOFF_SDC_FILE is used instead
~ Enable DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION for APU which fails after SDC updates.
~ Adjust timing checkers according to the new reported values
2023-09-05 16:25:24 +03:00
Mohamed Gaber
6a29379266 Add Banner for OpenLane 2 (#1966)
As OpenLane 1 approaches a feature freeze, people who want new features should be going there more.
2023-09-03 14:02:52 +03:00
Kareem Farid
a9942b78ec Correct default value of RUN_IRDROP_REPORT in documentation (#1959) 2023-08-30 13:41:49 +03:00
Kareem Farid
00caae2b31 Update PDK + Restore RC_LAYER variables (#1932)
~ `open_pdks` -> `e3b630d9b7c0e23615367d52c4f78b2d2ede58ac`
~ `WIRE_RC_LAYER` split back into `CLOCK_WIRE_RC_LAYER` and `DATA_WIRE_RC_LAYER`

Co-authored-by: Mohamed Gaber <me@donn.website>
2023-08-22 19:35:09 +03:00
Mohamed Gaber
17559fa562 CI Tweaks (#1951)
~ Fixed issue where token set for Volare may cause authentication issues by falling back to secrets.GITHUB_TOKEN
~ Update documentation version constraints to accommodate furo bug
2023-08-22 18:54:25 +03:00
Donn
b1fb228e31 Revert "Enhancements to variables related to SDC files (#1931)"
This reverts commit 7a5857a595.
2023-08-10 17:44:18 +03:00
Kareem Farid
7a5857a595 Enhancements to variables related to SDC files (#1931)
+ Warn when IMPLEMENTATION_SDC_FILE is not overwritten by the user.
+ Add SDC_IN and IMPLEMENTATION_SDC_FILE_DEFAULT to ignore list in ci Check Variables flow
~ Rename RCX_SDC_FILE to SIGNOFF_SDC_FILE.
~ Rename BASE_SDC_FILE to IMPLEMENTATION_SDC_FILE.
~ Always use IMPLMEMENTATION_SDC_FILE instead of CURRENT_SDC except during signoff stage
2023-08-10 16:47:52 +03:00
Kareem Farid
37cea3e30f Remove CTS_TOLERANCE (#1928)
~ Mark CTS_TOLERANCE as removed
~ Changes related to formatting consistency in variable documentation
2023-08-09 13:35:21 +00:00
Mohamed Gaber
157a650587 Update Documentation (#1917)
+ Added `make docs` target to primary Makefile to generate documentation
~ Update documentation dependencies
~ Updated `tcl.py` to handle JSON lists of elements including whitespace by joining them with a comma (unless one of the elements already contains a comma), resolving odd JSON syntax
~ Re-organized and re-order configuration variables and edited descriptions for general consistency as well as adding anchors
~ Update all documentation dependencies
~ Fixed a number of broken links
- Remove dependency on `docutils` and `sphinx-autobuild` (both unused)
- Remove two of the custom documentation extensions
2023-07-25 13:02:39 +03:00
Kareem Farid
c43cd3cbae Move CI designs to a separate repository (#1867)
~ Move test designs to a separate repository and add it as a submodule.
~ Adjust test set to refer to designs in submodule.
~ Change design_dir in `run_tests.py` for artifact upload in the CI.
~ Fix fail condition on design name mismatch in `compare_regression_reports.py`
~ Print a better error message for design name mismatch mentioned previously. 
~ Change regression benchmark to point reflect submodule change. 
~ Change documentation to reflect new paths of designs.
+ Add aes_user_project_wrapper to ci designs to test EXTRA_SPEFS.
+ Add a step in CI workflow to replace `/` with `_` in design name for artifact upload.
2023-07-13 12:39:52 +03:00
Mohamed Gaber
2735f41574 PDK Variable Consistency (#1892)
~ Classified PDK variables by user modifiability
~ `SYNTH_MAX_FANOUT` -> Moved into PDK as `MAX_FANOUT_CONSTRAINT`
~ `SYNTH_MAX_TRAN` -> Moved into PDK as `MAX_TRANSITION_CONSTRAINT`
~ `SYNTH_CAP_LOAD` -> `OUTPUT_CAP_LOAD`
- Removed `DEFAULT_MAX_TRAN` from PDK (unused)
2023-07-12 17:05:03 +03:00
Kareem Farid
ed5647b8c8 Undocumented Variable CI Workflow
Script uses regular expressions to create a set of documents variables and a set of used variables and compare them against each other. Some variables are internal, unexposed and others. These variables are whitelisted. See https://github.com/The-OpenROAD-Project/OpenLane/issues/1889

\+ Add documentation for `QUIT_ON_XOR_ERROR`
2023-07-12 14:38:52 +03:00
Kareem Farid
c57c6c66bb Cleanup Deprecated Variable Documentation (#1887)
~ Rename `antenna.log` to `arc.log` and `magic_antenna.log` to avoid confusion
~ Separate PDK porting instructions and PDK variables
~ Add deprecated variables to documentation
~ Make existing deprecated variable documentation formatting-consistent and with replacement instructions
- Remove defaults from deprecated variables (they don't have any)
- Remove `LIB_MIN`/`LIB_MAX`: enough time has passed and PDK variables are annoying to deprecate

Co-authored-by: Donn <me@donn.website>
2023-07-09 15:14:34 +03:00
Mohamed Gaber
21f54716ea Add missing documentation
Signed-off-by: Mohamed Gaber <donn@efabless.com>
2023-07-07 21:43:47 +03:00
Kareem Farid
aeef4d0572 Enhance IR Drop Analysis (#1864)
+ Add `VSRC_LOC_FILES`
+ Fix IR drop analysis flow
+ Consistent default NONE in configuration.md
2023-06-22 12:53:38 +03:00
Kareem Farid
54b233a6be Wrap splitnets and insbuf around SYNTH_SPLITNETS and SYNTH_BUFFER_DIRECT_WIRES (#1857)
Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
2023-06-19 13:42:22 +03:00
Kareem Farid
a3c416c54e Linter(Verilator) enhancements (#1837)
~ generalize verilator variables:
  QUIT_ON_VERILATOR_ERRORS -> QUIT_ON_LINTER_ERRORS
  QUIT_ON_VERILATOR_WARNINGS -> QUIT_ON_LINTER_WARNINGS
  VERILATOR_RELATIVE_INCLUDES -> LINTER_RELATIVE_INCLUDES
  RUN_VERILATOR -> RUN_LINTER
+ add LINTER_INCLUDE_PDK_MODELS
+ add LINTER_DEFINES
+ include verilator in ci tool updater
- do not include pdk verilog models using -I
- remove workaround for verilator std error
- disallow timing constructs. Print an error to the user to remove or guard them.
2023-06-19 11:47:56 +03:00
Kareem Farid
2e6954e75c magic lef write updates (#1850)
~ default to lef/def in order to generate lef with pin direction (and much faster than gds) 
~ bump magic version
~ restore `drc off` in `lef.tcl` that was removed in an older PR
~ record a separate magic lef write runtime
- remove unneeded `cellname` command from `lef.tcl`
+ add lef nocheck for power connections for antenna area calculation
2023-06-18 14:31:44 +03:00
Kareem Farid
0bd45a23aa Add TRISTATE_CELL_PREFIX (#1796)
Fix condition of SYNTH_CHECKS_ALLOW_TRISTATE for hand-instantiated tristate buffers
2023-06-13 20:36:04 +03:00
Kareem Farid
6bb1e0dd91 Add gui.py (#1824)
\+ Add `gui.py`. Adding the help message here:
```
Usage: gui.py [OPTIONS] RUN_DIR

  View specified layout from run_dir using supported viewers

Options:
  --viewer [klayout|openroad]     Viewer option  [default: openroad]
  -f, --format [def|odb|gds]      Layout format to view  [default: odb]
  -s, --stage [cts|floorplan|placement|routing|signoff]
                                  Optionally specify which stage to view
  --help                          Show this message and exit.
```

\+ Mount HOME directory when running `make mount`.
\+ Add `-congestion_report_file` to steps that call global routing
2023-05-30 17:44:50 +03:00
Mohamed Gaber
bee7c9d240 Fix Max Transition Time Usage (#1826)
+ Add `SYNTH_MAX_TRAN` to `base.sdc` (if set)
~ Fix syntax error in `all.tcl`
- Removed attempt(s) to calculate a default value for `SYNTH_MAX_TRAN` in `all.tcl`, `openroad/cts.tcl` and `yosys/synth.tcl`
2023-05-29 18:14:34 +03:00
Kareem Farid
5880f35897 Read multi-corner libs while running resizer and CTS (#1804)
+ add `RSZ_MULTICORNER_LIB`: a flag to read multicorner libs during resizer optimizations
+ add `RSZ_LIB_FASTEST`: defaults to `LIB_FASTEST`
+ add `RSZ_LIB_SLOWEST`: defaults to `LIB_SLOWEST`
+ add `LIB_CTS_SLOWEST`
+ add `LIB_CTS_FASTEST`
+ add `CTS_MULTICONER_LIB`
~ in `read_libs`, in `scripts/openroad/common/io.tcl`, iterate over each each corner definition to allow for reading multiple files for each corner.
~ replace `-override_libs` and `-multi_corner_libs` by `-lib_fastest`, `-lib_slowest` and `-lib_typical` and modify resizer and cts tcl scripts accordingly
~ don't make copies of files in `LIB_SYNTH_COMPLETE` for `RSZ_LIB`, instead point to the original files
2023-05-24 17:30:26 +03:00
Kareem Farid
ee14c3eb23 Add RSZ_DONT_TOUCH list (#1798) 2023-05-23 16:19:10 +03:00
Kareem Farid
0d205c6192 Rename PDN_CFG to FP_PDN_CFG (#1773)
~ Rename PDN_CFG to FP_PDN_CFG
2023-04-27 13:21:06 +02:00
Kareem Farid
6b97e2c444 Moving, Renaming and Documenting Config. Variables (#1764)
Renamed Variables:
```
CLOCK_TREE_SYNTH -> RUN_CTS
FP_PDN_RAILS_LAYER -> FP_PDN_RAIL_LAYER
FP_PDN_UPPER_LAYER, FP_PDN_LOWER_LAYER -> FP_PDN_HORIZONTAL_LAYER, FP_PDN_VERTICAL_LAYER
```
Removed from default configuration:
```
RCX_CORNER_COUNT
RCX_MAX_RESISTANCE		
RCX_COUPLING_THRESHOLD		
RCX_CC_MODEL	
RCX_CONTEXT_DEPTH
```
Added documentation:
```
FP_PDN_CFG
FP_PDN_HSPACING
FP_PDN_VSPACING
FP_TAPCELL_DIST
DFF_LIB_SYNTH
DIODE_CELL_PIN
DIODE_CELL
STD_CELL_GROUND_PINS
CARRY_SELECT_ADDER_MAP
FULL_ADDER_MAP
STD_CELL_LIBRARY_CDL
LAYERS_RC
VIAS_RC
SYNTH_DEFINES
STA_REPORT_POWER
FP_PDN_ENABLE_GLOBAL_CONNECTIONS
PL_RESIZER_TIE_SEPERATION
QUIT_ON_HOLD_VIOLATIONS
QUIT_ON_SETUP_VIOLATIONS
QUIT_ON_TIMING_VIOLATIONS
```
Moved to pdk configuration:
```
FP_PDN_VOFFSET
FP_PDN_VPITCH
FP_PDN_HOFFSET
FP_PDN_HPITCH
```
\- Remove unneeded usage of `PL_TARGET_DENSITY_CELLS`

Addresses https://github.com/The-OpenROAD-Project/OpenLane/issues/1325
2023-04-26 10:39:25 +02:00
Kareem Farid
02a096e7af Integrate Verilator (#1760)
+ Add verilator check before synthesis
+ Add QUIT_ON_VERILATOR_ERRORS
+ Add QUIT_ON_VERILATOR_WARNINGS
+ Add VERILATOR_RELATIVE_INCLUDES
+ Only load verilog models for selected PDKs and warn the user about unsupported PD
2023-04-19 14:22:25 +02:00
Sean Cross
00aff7d51f Document -gui option (#1759) 2023-04-17 11:03:56 +02:00
Mohamed Gaber
630aa1ff3c Reorganize Timing Reports (#1704)
~ Add reports for timing multi-corner STA across all process corners
~ Sort min/max report outputs by slack
~ Combine Slew, Fanout, Capacitance and Annotation Checks into one `_sta.checks.rpt`
~ Combine TNS, WNS, Worst_Slack into one `_sta.summary.rpt`
~ Fix regression in #1675 where logs were renamed and reports were not getting generated for some steps
~ Update documentation
\- Remove UMich ECO timing report vestiges

---
Based on feedback from @shalan, Fixes #875
2023-04-16 20:56:30 +02:00
Mohamed Gaber
1f21398e5c Remove -from and -to (#1757) 2023-04-16 20:52:59 +02:00
Kareem Farid
49c28da7bb or_issue.py doc update and fix (#1733) 2023-04-11 01:24:54 +02:00
Kareem Farid
97fc540e76 pdk_structure.md updates (#1734)
~ typo fix
- remove deprecated pdn PDK config
2023-04-11 01:24:14 +02:00
Kareem Farid
06603f4674 io_place.py pin separation constraints adjustments (#1723)
~ set min distance in cfg file instead of using `FP_IO_MIN_DISTANCE`
~ don't quit when min distance < legal min distance and use legal min distance. by definition if min distance is illegal it is "minimum" and we can use a higher value
~ `min_distance` is not min spacing - adjust legal tracks in `io_place.py` under that assumption
2023-04-10 14:15:58 +02:00
Kareem Farid
674456fad6 Magic LEF write updates (#1728)
+ add wrapper.tcl to capture magic errors ported from openlane2
~ use lef/def or gds instead of mag to write a lef through MAGIC_LEF_WRITE_USE_GDS
~ print lef write log file path
2023-04-10 14:09:07 +02:00
Kareem Farid
0925f7506f Add Tri-State Logic Exception to Synthesis Checks (#1708)
Fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1701

\~ Move Yosys check quitting entirely to Python script
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)

\+ Add `SYNTH_CHECKS_ALLOW_TRISTATE` that allows tristate buffers in yosys `check`
\~ Fix wrong default value of `RUN_HEURISTIC_DIODE_INSERTION` in documentation
\~ Move Yosys check quitting entirely to Python script, can ignore tristate buffer-related warnings
\~ Update DRC rosetta to use streams instead of in-memory translation (for most of them)
2023-04-06 13:03:00 +02:00
Kareem Farid
8a4b1e7f06 Hierarchical Static Timing Analysis (#1675)
\+ Add `EXTRA_SPEFS`
\+ Use `VERILOG_FILES_BLACKBOX` in sta. Allow skipping a file by adding a comment `/// sta-blackbox`
\+ Detect blackboxed modules in typical-corner STA during sign off and warn the user about it
\+ Add `run_sta_script` used in multicorner sta
\+ Support sta in `or_issue.py`
\+ Support sta in `run_tcl_script`
\+ Check if regex defined in `FP_PDN_MACRO_HOOKS` has a match. Fixes https://github.com/The-OpenROAD-Project/OpenLane/issues/1599
\~ Wrap `set_global_connections` around a flag since it is not supported by opensta
\~ Run multicorner sta using standalone sta application for hierarchical
sta support
\~ Move `sta_multi_corner.tcl` to `scripts/openroad/sta/multi_corner.tcl`
\~ Don't delete target directory of `-save` for multicorner spef files
\~ Merge multi_corner sta and single corner into one script.
\~ Split `RUN_STANDALONE` embedded inside openroad steps, which calls sta after, to another sta step run after said openroad step
\- Remove `report_design_area` in `multi_corner.tcl` since it is not supported by standalone OpenSTA 
\- Remove `scripts/openroad/sta.tcl`
2023-04-05 23:58:56 +02:00
Kareem Farid
90c63712e5 Enhance Synthesis Exit Checks (#1698)
~ In `yosys`, call `check -assert` at the correct stage. This requires expanding `yosys` built-in command `synth` to its original sub-commands found in https://github.com/YosysHQ/yosys/blob/master/techlibs/common/synth.cc and inject `check -assert` in the middle of the expanded command. Experimentally, this was the only way to properly capture used wires that do not have a driver.

Additional synthesis checkers guarded with `QUIT_ON_SYNTH_CHECKS`:
\+ Add `check_latches`
\+ Add `check_out_of_bound`
\+ Add `check_resizing_cell_port`

~ Fix a "resizing cell port" error in `APU` design
~ Fix a "used but has no driver" error in `tests/912`
2023-03-28 14:14:03 +02:00
Mohamed Gaber
d70884942e CI Updates (#1690)
~ Change various Secrets to new Variables feature
~ Rename regression results by PDK and SCL
~ Test sets and the CI now incorporate the SCL
~ Minor adjustments to flow scripts
- Removed outdated regression results
2023-03-27 22:28:50 +02:00
Kareem Farid
2e09573fff Diode Insertion Overhaul (#1686)
- Deprecate DIODE_INSERTION_STRATEGY.
- Remove DIODE_INSERTION_STRATEGY 2, 1, and 5
+ Add GRT_REPAIR_ANTENNAS
+ Add HEURISTIC_ANTENNA_THRESHOLD
+ Add RUN_HEURISTIC_DIODE_INSERTION
+ Add DIODE_ON_PORTS
+ Add HEURISITIC_ANTENNA_INSERTION_MODE
~ Update benchmark results for SW_HD
~ Apply DIODE_PADDING in dpl_cell_pad which also runs after RUN_HEURISTIC_DIODE_INSERTION

run_designs.py:
  ~ Change default config to `config` instead of `config.json` to allow for designs with
  tcl default config
  ~ Change logging format
  + Print SUCCESS when a design is finished
  ~ Use extra parameters `params.keys()` instead of `ConfigHandler.get_header()` to build
   report csv header. This fixes inconsistencies between csv header and values reported

compare_regression_design.py:
  ~ Change metric name antenna_violations -> pin_antenna_violations
  ~ Handle "bad" encoding of csv report files
  ~ Quit when a report is perceived as invalid
  ~ Don't print output file name to stderr
  
compare_regression_reports.py:
  ~ Change metric name antenna_violations -> pin_antenna_violation
  ~ Handle "bad" encoding of csv report files

config.py:
  ~ Sort result from get_config_for_run and configuration_values for consistency
  ~ All get_config_for_run to get the full config
  
~ Fix antenna violations net extraction in `extract_antenna_violators.py`
~ Fix fetching antenna violation count in `generate_reports.py`

report.py:
  ~ Split "metric" antenna_violations to pin_antenna_violations and
  net_antenna_violations as reported by openroad antenna checker
  ~ Add Non-phyCells 
  ~ Add TotalCells
  ~ Rename cell_count to synth_cell_count to avoid confusion with TotalCells
  ~ Calculate cells_per_mm based on Non-phyCells instead of synth_cell_count
  ~ Rename
2023-03-27 20:30:59 +02:00
Mohamed Gaber
e5a7a09769 Rework Placement (#1684)
+ Add warning when attempting to run Sylvain's script without `DPL_CELL_PADDING` >= 0
+ Add warning when DPL_CELL_PADDING is set to greater than GPL_CELL_PADDING
~ Update PDK, changing the default values of GPL/DPL cell padding to `0`
~ **Use $HOME/.volare as the default PDK location**
~ `PL_TARGET_DENSITY` incorporates value of `GPL_CELL_PADDING` in calculation
~ Updated various config files to handle new default padding options
~ CI bugfixes + support for Volare 0.7.1
2023-03-22 15:29:01 +02:00
Mohamed Hosni
9b77c207f1 Change the default value of QUIT_ON_SYNTH_CHECKS to 1 (#1687) 2023-03-21 15:52:12 +02:00
Mohamed Gaber
8433bc03f8 Exit Cleanup (#1685)
~ Move `QUIT_ON` variables outside of checker functions
~ Move final timing checks to a flow step: `run_timing_check_step`
~ Replace a couple of loose `file exists` with `assert_files_exist` calls
~ Replace all `flow_fail` across the flow with `throw_error`, which behaves accordingly:
    * If running an interactive script, `flow_fail` is called
    * Else, the errors are propagated upwards, where `flow.tcl` is to catch it
~ Rename `try_catch` to `try_exec` as it now propagates the error, with translation behavior
- Remove UMich experimental ECO flow
2023-03-21 13:58:58 +02:00
Mohamed Hosni
a664c0e162 More strict antenna violations repair (#1671)
\+ Add `GRT_ANT_MARGIN`
\~  Increase `GRT_ANT_ITERS` to `15`

Signed-off-by: Mohamed Hosni <112901987+mo-hosni@users.noreply.github.com>
2023-03-02 13:15:42 +02:00
Mohamed Hosni
93c8d84c0d Add repair_design for global routing (#1670)
\+ Add run_resizer_design_routing before run_resizer_timing_routing
Co-authored-by: kareefardi <kareem.farid@efabless.com>
2023-03-02 12:55:32 +02:00