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analogdevicesinc/ hdl
Verilog 0 0
HDL libraries and projects
analog-devices fpga hacktoberfest hdl jesd204b verilog
Updated 2026-05-29 18:37:07 +08:00
lnis-uofu/ OpenFPGA
Verilog 0 0
An Open-source FPGA IP Generator
fpga fpga-soc
Updated 2026-05-24 13:29:26 +08:00
cliffordwolf/ picorv32
Verilog 0 0
PicoRV32 - A Size-Optimized RISC-V CPU
Updated 2024-06-17 14:20:13 +08:00
SI-RISCV/ e200_opensource
Verilog 0 0
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
china core cpu nuclei risc-v ultra-low-power verilog
Updated 2021-03-24 17:38:39 +08:00
onchipuis/ mriscv
Verilog 0 0
A 32-bit Microcontroller featuring a RISC-V core
Updated 2018-02-28 22:21:41 +08:00
ridecore/ ridecore
Verilog 0 0
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Updated 2017-07-12 17:42:45 +08:00
rgwan/ kamikaze
Verilog 0 0
Light-weight RISC-V RV32IMC microcontroller core.
Updated 2017-03-04 13:49:52 +08:00
KestrelComputer/ polaris
Verilog 0 0
RISC-V RV64IS-compatible processor for the Kestrel-3
Updated 2016-12-13 14:18:43 +08:00
qmn/ riscv-invicta
Verilog 0 0
A simple RISC-V core, described with Verilog
Updated 2013-06-02 05:43:46 +08:00