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logisim-evolution/ logisim-evolution

Java 0 0

Digital logic design tool and simulator

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Updated 2026-05-30 14:01:13 +08:00

analogdevicesinc/ hdl

Verilog 0 0

HDL libraries and projects

analog-devices fpga hacktoberfest hdl jesd204b verilog

Updated 2026-05-29 18:37:07 +08:00

lnis-uofu/ OpenFPGA

Verilog 0 0

An Open-source FPGA IP Generator

fpga fpga-soc

Updated 2026-05-24 13:29:26 +08:00

open-sdr/ openwifi

C 0 0

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

802-11 ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm openwifi sdr software-defined-radio verilog wifi xilinx xilinx-fpga zynq

Updated 2026-05-21 18:28:51 +08:00

SpinalHDL/ VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2026-02-11 17:06:28 +08:00

tommythorn/ yarvi

Roff 0 0

Yet Another RISC-V Implementation

fpga fpga-soc risc-v riscv riscv32 verilog

Updated 2024-09-22 07:51:52 +08:00