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SpinalHDL/ VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2026-02-11 17:06:28 +08:00

sergeykhbr/ riscv_vhdl

C++ 0 0

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cpu debugger qt riscv simulator soc systemc vhdl

Updated 2025-07-16 20:19:59 +08:00

RoaLogic/ RV12

SystemVerilog 0 0

RISC-V CPU Core

32-bit 64bit cpu risc-v

Updated 2025-06-25 04:44:51 +08:00

SI-RISCV/ e200_opensource

Verilog 0 0

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

china core cpu nuclei risc-v ultra-low-power verilog

Updated 2021-03-24 17:38:39 +08:00