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logisim-evolution/ logisim-evolution

Java 0 0

Digital logic design tool and simulator

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Updated 2026-05-30 14:01:13 +08:00

SpinalHDL/ VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2026-02-11 17:06:28 +08:00

sergeykhbr/ riscv_vhdl

C++ 0 0

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cpu debugger qt riscv simulator soc systemc vhdl

Updated 2025-07-16 20:19:59 +08:00

skordal/ potato

VHDL 0 0

A simple RISC-V processor for use in FPGA designs.

processor risc-v vhdl

Updated 2024-08-19 18:39:31 +08:00