Kareem Farid 2e09573fff Diode Insertion Overhaul (#1686)
- Deprecate DIODE_INSERTION_STRATEGY.
- Remove DIODE_INSERTION_STRATEGY 2, 1, and 5
+ Add GRT_REPAIR_ANTENNAS
+ Add HEURISTIC_ANTENNA_THRESHOLD
+ Add RUN_HEURISTIC_DIODE_INSERTION
+ Add DIODE_ON_PORTS
+ Add HEURISITIC_ANTENNA_INSERTION_MODE
~ Update benchmark results for SW_HD
~ Apply DIODE_PADDING in dpl_cell_pad which also runs after RUN_HEURISTIC_DIODE_INSERTION

run_designs.py:
  ~ Change default config to `config` instead of `config.json` to allow for designs with
  tcl default config
  ~ Change logging format
  + Print SUCCESS when a design is finished
  ~ Use extra parameters `params.keys()` instead of `ConfigHandler.get_header()` to build
   report csv header. This fixes inconsistencies between csv header and values reported

compare_regression_design.py:
  ~ Change metric name antenna_violations -> pin_antenna_violations
  ~ Handle "bad" encoding of csv report files
  ~ Quit when a report is perceived as invalid
  ~ Don't print output file name to stderr
  
compare_regression_reports.py:
  ~ Change metric name antenna_violations -> pin_antenna_violation
  ~ Handle "bad" encoding of csv report files

config.py:
  ~ Sort result from get_config_for_run and configuration_values for consistency
  ~ All get_config_for_run to get the full config
  
~ Fix antenna violations net extraction in `extract_antenna_violators.py`
~ Fix fetching antenna violation count in `generate_reports.py`

report.py:
  ~ Split "metric" antenna_violations to pin_antenna_violations and
  net_antenna_violations as reported by openroad antenna checker
  ~ Add Non-phyCells 
  ~ Add TotalCells
  ~ Rename cell_count to synth_cell_count to avoid confusion with TotalCells
  ~ Calculate cells_per_mm based on Non-phyCells instead of synth_cell_count
  ~ Rename
2023-03-27 20:30:59 +02:00
2023-03-22 15:29:01 +02:00
2023-03-22 15:29:01 +02:00
2023-03-23 15:55:57 +02:00
2023-03-27 20:30:59 +02:00
2023-03-27 20:30:59 +02:00
2023-03-21 13:58:58 +02:00
2020-10-08 17:56:42 +02:00
2022-03-29 15:10:54 +02:00
2023-03-27 20:30:59 +02:00
2022-06-02 00:06:03 +02:00
2020-07-20 13:03:23 -07:00
2023-03-22 15:29:01 +02:00
2022-06-07 08:43:35 +02:00

OpenLane

Open in Colab License: Apache 2.0 GitHub Actions Status Badge Documentation Build Status Badge Invite to the Open Source Silicon Slack Python Code Style: black

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, KLayout and a number of custom scripts for design exploration and optimization. The flow performs all ASIC implementation steps from RTL all the way down to GDSII.

You can check out the documentation, including in-depth guides and reference manuals at ReadTheDocs.

Quick-start Guide

If you just want to try OpenLane out, try this Colaboratory by our friends at Google and ChipsAlliance. It's an online Python-based utility, and the best part is, you don't need to install anything.

Installation, the short version

The short version is, to install the OpenLane environment...

On Windows, install and launch the Windows Subsystem for Linux before doing anything. We recommend and provide instructions for Ubuntu 20.04.

On macOS, get brew.

  1. Get Docker (or a compatible container engine)
  2. Get Python 3.6 or higher (macOS | Ubuntu)
    • On Ubuntu, you may also need to install venv: apt-get install python3-venv, and pip: apt-get install python3-pip.
  3. Get git (macOS | Ubuntu)
  4. Get GNU Make (macOS | Ubuntu)

Run the following commands in your command-line prompt:

cd $HOME
git clone https://github.com/The-OpenROAD-Project/OpenLane
cd OpenLane
make
make test

If everything's gone smoothly, that's it. OpenLane is set up on your computer. To enter the OpenLane environment, cd $HOME/OpenLane and then make mount.

Installation, the long version

See the installation docs at https://openlane.readthedocs.io/en/latest/getting_started/installation/index.html.

Usage

After entering the OpenLane environment, you can start hardening chips: the following command, for example, runs the included spm design.

./flow.tcl -design spm

Need more help?

You can join the Open Source Silicon Slack, where you can ask thousands of other open source hardware enthusiasts for help with setting up or running OpenLane.

License

The Apache License, version 2.0.

Docker images distributed by Efabless Corporation under the same license.

Binaries in OpenLane distributions may fall under stricter open source licenses.

Description
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Readme Apache-2.0 1.7 GiB
Languages
Python 57.6%
Tcl 37.1%
Verilog 2.7%
Makefile 0.8%
Nix 0.8%
Other 1%