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actions/ download-artifact

TypeScript 0 0

Updated 2026-03-17 21:33:43 +08:00

heitzmann/ gdstk

C++ 0 0

cad cpp eda gdsii microfabrication oasis polygons python svg

Updated 2026-03-14 02:46:25 +08:00

chipsalliance/ verible

C++ 0 0

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc

Updated 2026-03-13 23:14:08 +08:00

OSCC-Project/ iEDA

C++ 0 0

Updated 2026-03-11 16:36:09 +08:00

The-OpenROAD-Project/ abc

C 0 0

ABC: System for Sequential Logic Synthesis and Formal Verification

Updated 2026-03-01 12:45:30 +08:00

librecell/ lclayout

Python 0 0

Updated 2026-02-17 15:25:28 +08:00

antlr/ antlr4

Java 0 0

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

antlr antlr4 cpp csharp dart golang grammar java javascript language-recognition parse parser-generator parsing php python swift

Updated 2026-02-17 05:29:09 +08:00

SpinalHDL/ VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2026-02-11 17:06:28 +08:00

actions/ first-interaction

TypeScript 0 0

Updated 2026-01-22 07:53:13 +08:00

LibrEDA/ libreda-rs-workspace

Rust 0 0

Updated 2026-01-18 04:21:35 +08:00

LibrEDA/ liberty-io

Rust 0 0

Updated 2026-01-18 04:21:06 +08:00

efabless/ openlane2

Python 0 0

The next generation of OpenLane, rewritten from scratch with a modular architecture

asic drc eda flow flows gdsii gf180mcu lvs openlane openroad pdk pnr rtl-to-gds silicon sky130 sta verilog vlsi

Updated 2025-12-02 20:25:48 +08:00

LibrEDA/ pargraph

Rust 0 0

Updated 2025-11-20 17:25:33 +08:00

LibrEDA/ interp

Rust 0 0

Updated 2025-11-13 23:36:20 +08:00

LibrEDA/ libreda-pnr

Rust 0 0

Updated 2025-11-13 23:35:53 +08:00

LibrEDA/ electron-placer

Rust 0 0

Updated 2025-11-13 23:35:27 +08:00

LibrEDA/ libreda-sta

Rust 0 0

Updated 2025-11-12 04:53:34 +08:00

LibrEDA/ mycelium-router

Rust 0 0

Updated 2025-11-10 15:16:50 +08:00

LibrEDA/ libreda-logic

Rust 0 0

Updated 2025-11-10 15:14:10 +08:00

lilin5819/ action_test

0 0

Updated 2025-11-09 05:50:44 +08:00