Repositories Users Organizations
Filter
Sort
opencv-library/ opencv
CMake 0 0
Computer Vision and Image Processing Library
Updated 2024-12-21 22:52:29 +08:00
LibrEDA/ libreda-structural-verilog
Rust 0 0
Updated 2024-12-06 20:47:49 +08:00
LibrEDA/ libreda-examples
Coq 0 0
Updated 2024-12-06 19:52:43 +08:00
syntacore/ scr1
SystemVerilog 0 0
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog
Updated 2024-11-15 22:22:48 +08:00
google/ skywater-pdk
Python 0 0
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
asic asic-library eda magic openram openroad pdk skywater
Updated 2024-10-28 17:51:43 +08:00
tommythorn/ yarvi
Roff 0 0
Yet Another RISC-V Implementation
fpga fpga-soc risc-v riscv riscv32 verilog
Updated 2024-09-22 07:51:52 +08:00
LibrEDA/ iron-shapes-booleanop
Rust 0 0
Updated 2024-09-18 15:51:16 +08:00
LibrEDA/ libreda-regionsearch
Rust 0 0
Updated 2024-09-14 17:21:38 +08:00
skordal/ potato
VHDL 0 0
A simple RISC-V processor for use in FPGA designs.
processor risc-v vhdl
Updated 2024-08-19 18:39:31 +08:00
cliffordwolf/ picorv32
Verilog 0 0
PicoRV32 - A Size-Optimized RISC-V CPU
Updated 2024-06-17 14:20:13 +08:00
LibrEDA/ splay
Rust 0 0
Updated 2024-06-06 14:51:52 +08:00
LibrEDA/ iron-shapes-algorithms
Rust 0 0
Updated 2024-06-05 01:24:36 +08:00
LibrEDA/ libreda-stream-parser
Rust 0 0
Updated 2024-05-30 05:19:33 +08:00
LibrEDA/ steiner-tree
Rust 0 0
Updated 2024-05-30 05:04:33 +08:00
LibrEDA/ pages
HTML 0 0
Updated 2024-03-28 20:25:12 +08:00
vlsi-eda/ coriolis
PostScript 0 0
Coriolis VLSI CAD Tools
Updated 2023-11-23 19:38:04 +08:00
LibrEDA/ arboreus-cts
Rust 0 0
Updated 2023-11-19 03:06:36 +08:00
LibrEDA/ libreda-book
Shell 0 0
Updated 2023-08-16 19:17:37 +08:00
lowrisc/ lowrisc-chip
SystemVerilog 0 0
The root repo for lowRISC project and FPGA demos.
Updated 2023-08-03 21:48:32 +08:00
LibrEDA/ libreda-synth-exact
Rust 0 0
Updated 2023-07-13 04:44:08 +08:00